A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.

An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal oxide semiconductor (LDMOS) device may be present in the lateral device region, wherein a drift region of the LDMOS device has a length that is parallel to an upper surface of the substrate in which the LDMOS device is formed. A vertical field effect transistor (VFET) device may be present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel.

The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.

A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench

A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, including forming a pinch-off layer on one or more vertical fin segments, wherein the pinch-off layer has a thickness on the sidewalls of the one or more vertical fin segments, forming a trench mask layer on predetermined portions of the pinch-off layer, removing portions of the pinch-off layer not covered by the trench mask layer, where the removed portions of the pinch-off layer exposes underlying portions of the substrate, and removing at least a portion of the substrate to form one or more isolation region trenches, where the distance of the sidewall of one of the one or more isolation region trenches to an adjacent vertical fin segment is determined by the thickness of the pinch-off layer.

A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, including forming a pinch-off layer on one or more vertical fin segments, wherein the pinch-off layer has a thickness on the sidewalls of the one or more vertical fin segments, forming a trench mask layer on predetermined portions of the pinch-off layer, removing portions of the pinch-off layer not covered by the trench mask layer, where the removed portions of the pinch-off layer exposes underlying portions of the substrate, and removing at least a portion of the substrate to form one or more isolation region trenches, where the distance of the sidewall of one of the one or more isolation region trenches to an adjacent vertical fin segment is determined by the thickness of the pinch-off layer.

A method for forming the semiconductor device that includes forming a plurality of composite fin structures across a semiconductor substrate including an active device region and an isolation region. The composite fin structures may include a semiconductor portion over the active device region and a dielectric portion over the isolation region. A gate structure can be formed on the channel region of the fin structures that are present on the active regions of the substrate, and the gate structure is also formed on the dielectric fin structures on the isolation regions of the substrate. Epitaxial source and drain regions are formed on source and drain portions of the fin structures present on the active region, wherein the dielectric fin structures support the gate structure over the isolation regions.

A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.

Deterioration in reliability is prevented regarding a semiconductor device. The deterioration is caused when an insulating film for formation of a sidewall is embedded between gate electrodes at the time of forming sidewalls having two kinds of different widths on a substrate. A sidewall-shaped silicon oxide film is formed over each sidewall of a gate electrode of a low breakdown voltage MISFET and a pattern including a control gate electrode and a memory gate electrode. Then, a silicon oxide film beside the gate electrode is removed, and a silicon oxide film is formed on a semiconductor substrate, and then etchback is performed. Accordingly, a sidewall, formed of a silicon nitride film and the silicon oxide film, is formed beside the gate electrode, and a sidewall, formed of the silicon nitride film and the silicon oxide films, is formed beside the pattern.

The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.