A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

A method includes depositing a multi-layer stack on a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a dummy gate on the multi-layer stack; forming a first spacer on a sidewall of the dummy gate; performing a first implantation process to form a first doped region, the first implantation process having a first implant energy and a first implant dose; performing a second implantation process to form a second doped region, where the first doped region and the second doped region are in a portion of the channel layers uncovered by the first spacer and the dummy gate, the second implantation process having a second implant energy and a second implant dose, where the second implant energy is greater than the first implant energy, and where the first implant dose is different from the second implant dose.

A method of fabricating a semiconductor device includes forming first gate structure and a second gate structure over a core device region of a substrate. The method further includes forming stressors at opposite sides of the first gate structure. The method further includes doping the stressors to form a first source region and a first drain region of a first device. The method further includes doping into the substrate and at opposite sides of the second gate structure to form a second source region and a second drain region of a second device, wherein the first source region, the first drain region, the second source region and the second drain region are of a same conductivity. The first source region includes a different material from the second source region.

A transistor including an oxide semiconductor, which has good on-state characteristics, and a high-performance semiconductor device including a transistor capable of high-speed response and high-speed operation. In the transistor including an oxide semiconductor, oxygen-defect-inducing factors are introduced (added) into an oxide semiconductor layer, whereby the resistance of a source and drain regions are selectively reduced. Oxygen-defect-inducing factors are introduced into the oxide semiconductor layer, whereby oxygen defects serving as donors can be effectively formed in the oxide semiconductor layer. The introduced oxygen-defect-inducing factors are one or more selected from titanium, tungsten, and molybdenum, and are introduced by an ion implantation method.

A method includes providing a substrate having a mesa, forming a first opening in the mesa, the first opening being surrounded by first inner sidewalls of the mesa exposed by the first opening. The method further includes etching from a first one of the first inner sidewalls of the mesa to form a first vertical recess, the first vertical recess having a wide end and a narrow end, with the narrow end defining a first vertically recessed channel region, and forming a first gate structure over the first vertically recessed channel region.

A thermal mixing process is employed to convert a portion of a silicon germanium alloy fin having a first germanium content and an overlying non-doped epitaxial silicon source material into a silicon germanium alloy source structure having a second germanium content that is less than the first germanium content, to convert another portion of the silicon germanium alloy fin and an overlying non-doped epitaxial silicon drain material into a silicon germanium alloy drain structure having the second germanium content, and to provide a tensile strained silicon germanium alloy fin portion having the first germanium content. A dopant is then introduced into the silicon germanium alloy source structure and into the silicon germanium alloy drain structure.

An etching method is disclosed. The etching method comprises providing on a substrate a structure comprising a recess region formed therein. The recess region includes an inner part and a mouth part whose width is less than that of the inner part. The etching method further comprises performing a clean-then-etch process to remove at least a portion of etching object formed outside the recess region. The performing a clean-then-etch process comprises performing a cleaning process to fill at least a portion of the recess region with a cleaning solution, and performing a wet etch process to the substrate in a state that the cleaning solution remains in the recess region.

A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a first gate structure on a first side of an active area and a second gate structure on a second side of the active area, where the first gate structure and the second gate structure share the active area. A method of forming the semiconductor arrangement includes forming a deep implant of the active area before forming the first gate structure, and then forming a shallow implant of the active area. Forming the deep implant prior to forming the first gate structure alleviates the need for an etching process that degrades the first gate structure. The first gate structure thus has a desired configuration and is able to be formed closer to other gate structures to enhance device density.

A method for forming a semiconductor device includes forming a first fin and a second fin on a substrate, the first fin arranged in parallel with the second fin, the first fin arranged a first distance from the second fin, the first fin and the second fin extending from a first source/drain region through a channel region and into a second source/drain region on the substrate. The method further includes forming a third fin on the substrate, the third fin arranged in parallel with the first fin and between the first fin and the second fin, the third fin arranged a second distance from the first fin, the second distance is less than the first distance, the third fin having two distal ends arranged in the first source/drain region. A gate stack is formed over the first fin and the second fin.

High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.