Diode includes first metal layer, coupled to p-type III-N layer and to first terminal, has a substantially equal lateral size to the p-type III-N layer. Central portion of light emitting region on first side and first metal layer includes first via that is etched through p-type portion, light emitting region and first part of n-type III-N portion. Second side of central portion of light emitting region that is opposite to first side includes second via connected to first via. Second via is etched through second part of n-type portion. First via includes second metal layer coupled to intersection between first and second vias. Electrically-insulating layer is coupled to first metal layer, first via, and second metal layer. First terminals are exposed from electrically-insulating layer. Third metal layer including second terminal is coupled to n-type portion on second side of light emitting region and to second metal layer through second via.

A contact to a semiconductor heterostructure is described. In one embodiment, there is an n-type semiconductor contact layer. A light generating structure formed over the n-type semiconductor contact layer has a set of quantum wells and barriers configured to emit or absorb target radiation. An ultraviolet transparent semiconductor layer having a non-uniform thickness is formed over the light generating structure. A p-type contact semiconductor layer having a non-uniform thickness is formed over the ultraviolet transparent semiconductor layer.

A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.

A quantum dot having core-shell structure, including a core formed of ZnO.sub.zS.sub.1-z of wurtzite crystal structure of hexagonal crystal system; a first shell covering the core, and formed of Al.sub.xGa.sub.yIn.sub.1-x-yN of wurtzite crystal structure of hexagonal crystal system; and a second shell covering the first shell, and formed of ZnO.sub.vS.sub.1-v of wurtzite crystal structure of hexagonal crystal system. At least one of v, x, y, and z is not zero and is not one; differences between the lattice constants along a-axis of the core, the first shell and the second shell are not greater than 1%; and the core, the first shell and the second shell form band offset structure of type II.

In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.

There is provided a method for manufacturing a nanostructure semiconductor light emitting device, including: forming a mask having a plurality of openings on a base layer; growing a first conductivity-type semiconductor layer on exposed regions of the base layer such that the plurality of openings are filled, to form a plurality of nanocores; partially removing the mask such that side surfaces of the plurality of nanocores are exposed; heat-treating the plurality of nanocores after partially removing the mask; sequentially growing an active layer and a second conductivity-type semiconductor layer on surfaces of the plurality of nanocores to form a plurality of light emitting nanostructures, after the heat treatment; and planarizing upper parts of the plurality of light emitting nanostructures such that upper surfaces of the nanocores are exposed.

A light emitting diode chip includes: a first conductive type semiconductor layer disposed on a substrate; a mesa disposed on the first conductive type semiconductor layer and including an active layer and a second conductive type semiconductor layer; an insulation layer covering the first conductive type semiconductor layer and the mesa, the insulation layer including at least one first opening exposing the first conductive type semiconductor layer and a second opening disposed on the mesa; a first pad electrode disposed on the insulation layer and electrically connected to the first conductive type semiconductor layer through the first opening; and a second pad electrode disposed on the insulation layer and electrically connected to the second conductive type semiconductor layer through the second opening. The first opening of the insulation layer includes a first region covered by the first pad electrode and a second region exposed outside the first pad electrode.

A light emitting device can include a GaN layer having a multilayer structure that can include an n-type layer, an active layer, and a p-type layer, the GaN layer having a first surface and a second surface; a conductive structure on the first surface of the GaN layer, the conductive structure includes a first electrode in contact with the first surface of the GaN layer, the first electrode is configured to reflect light from the active layer back through the second surface of the GaN layer; and a metal layer including Au, in which the metal layer serves as a first pad; a second electrode on the second surface of the GaN layer; and a second pad on the second electrode, in which a thickness of the second pad is about 0.5 m or higher.

Disclosed are a light emitting device, a method of manufacturing a light emitting device, a light emitting device package and a lighting system. The light emitting device includes a substrate; a first conductive semiconductor layer on the substrate; an active layer on the first conductive semiconductor layer; a second conductive semiconductor layer on the active layer; a contact layer on the second conductive semiconductor layer; an insulating layer on the contact layer; a first branch electrode electrically connected to the first conductive semiconductor layer; a plurality of first via electrodes connected to the first branch electrode and electrically connected to the first conductive semiconductor layer by passing through the insulating layer; a first pad electrode electrically connected to the first branch electrode; a second pad electrode contacts the contact layer by passing through the insulating layer; a second branch electrode connected to the second pad electrode and disposed on the insulating layer; and a plurality of second via electrodes provided through provided through the insulating layer to electrically connect the second branch electrode to the contact layer.

A light-emitting device is provided. The light-emitting device comprises a light-emitting stack comprising a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer. The light-emitting device further comprises a third semiconductor layer on the light-emitting stack and comprising a first sub-layer, a second sub-layer and a roughened surface, wherein the first sub-layer has the same composition as that of the second sub-layer, and the composition of the first sub-layer is with a different atomic ratio from that of the second sub-layer. A method for manufacturing the light-emitting device is also provided.