A light-emitting device includes: a rectangular shape with a 1.sup.st side, a 2.sup.nd side opposite to the 1.sup.st side, and a 3.sup.rd side connecting the 1.sup.st and the 2.sup.nd sides; a first electrode pad formed adjacent to the 3.sup.rd side; a second electrode pad formed adjacent to the 2.sup.nd side; a first extension electrode, extending from the first electrode pad in a direction away from the 3.sup.rd side and bended toward the 2.sup.nd side; and a second extension electrode, including a first and a second branches respectively extending from the second electrode pad; wherein a distance between the first electrode pad and the 3.sup.rd side is smaller than a distance between the second electrode pad and the 3.sup.rd side; wherein an end portion of the first branch includes a first arc bending to the 3.sup.rd side and a minimum distance between the first branch and the 1.sup.st side is smaller than a minimum distance between the second branch and the 1.sup.st side.

A light emitting element includes an n-side semiconductor layer, a p-side semiconductor layer, a plurality of holes, a first p-electrode, a second p-electrode and an n-electrode. The n-side semiconductor layer has a hexagonal shape in plan view. The p-side semiconductor layer has a hexagonal shape in plan view and provided over the n-side semiconductor layer. The holes are arranged in the p-side semiconductor layer so that the n-side semiconductor layer is exposed through the plurality of holes. The first p-electrode is in contact with the p-side semiconductor layer. The second p-electrode is arranged on the first p-electrode adjacent to a corner corresponding to one of vertices of the hexagonal shape. The second p-electrode has sides that are respectively parallel to sides defining the corner in plan view. The n-electrode is arranged over the first p-electrode and is electrically connected to the n-side semiconductor layer through the plurality of holes.

By controlling the luminance of light emitting element not by means of a voltage to be impressed to the TFT but by means of controlling a current that flows to the TFT in a signal line drive circuit, the current that flows to the light emitting element is held to a desired value without depending on the characteristics of the TFT. Further, a voltage of inverted bias is impressed to the light emitting element every predetermined period. Since a multiplier effect is given by the two configurations described above, it is possible to prevent the luminance from deteriorating due to a deterioration of the organic luminescent layer, and further, it is possible to maintain the current that flows to the light emitting element to a desired value without depending on the characteristics of the TFT.

A light-emitting device comprises a substrate having a top surface and a plurality of patterned units protruding from the top surface; and a light-emitting stack formed on the substrate and having an active layer with a first surface substantially parallel to the top surface, wherein one of the plurality of patterned units comprises a plurality of connecting sides constituting a polygon shape in a top view of the light-emitting device, the one of the plurality of patterned units comprises a vertex and a plurality of inclined surfaces respectively extending from the plurality of connecting sides, the plurality of inclined surfaces commonly join at the vertex in a cross-sectional view of the light-emitting device, the vertex being between the top surface of the substrate and the first surface of the active layer, and six of the plurality of patterned units forms a hexagon in the top view of the light-emitting device.

The present disclosure provides a light-emitting device and manufacturing method thereof. The light-emitting device comprising: a light-emitting stack; and a semiconductor layer having a first surface connecting to the light-emitting stack, a second surface opposite to the first surface, and a void; wherein the void comprises a bottom part near the first surface and an opening on the second surface, and a dimension of the bottom part is larger than the dimension of the opening.

A light emitting diode chip including a substrate and a light emitting diode element layer is provided. The substrate has a growth surface and a plurality of microstructures on the growth surface. An area of the growth surface occupied by the microstructures is A1 and an area of the growth surface not occupied by the micro-structures is A2, such that A1 and A2 satisfy the relation of 0.1A2/(A1+A2)0.5. The light emitting diode element layer is disposed on the growth surface of the substrate.

An apparatus for positioning micro-devices on a destination substrate includes a first support to hold a destination substrate, a second support to provide or hold a transfer body having a surface to receive an adhesive layer, a light source to generate a light beam, a mirror configured to adjustably position the light beam on the adhesive layer on the transfer body, and a controller. The controller is configured to cause the light source to generate the light beam and adjust the mirror to position the light beam on the adhesive layer so as to selectively expose one or more portions of the adhesive layer to create one or more neutralized portions. The transfer body and the destination substrate are moved away from each other and one or more micro-devices corresponding to the one or more neutralized portions of the adhesive layer remain on the destination substrate.

There is provided a nanostructure semiconductor light emitting device including a base layer formed of a first conductivity-type semiconductor, a first insulating layer disposed on the base layer and having a plurality of first openings exposing partial regions of the base layer, a plurality of nanocores disposed in the exposed regions of the base layer and formed of the first conductivity-type semiconductor, an active layer disposed on surfaces of the plurality of nanocores positioned to be higher than the first insulating layer, a second insulating layer disposed on the first insulating layer and having a plurality of second openings surrounding the plurality of nanocores and the active layer disposed on the surfaces of the plurality of nanocores, and a second conductivity-type semiconductor layer disposed on the surface of the active layer positioned to be higher than the second insulating layer.

A display device with a semiconductor layer sequence includes an active region provided for generating radiation and a plurality of pixels. The display device also includes a carrier. The active region is arranged between a first semiconductor layer and a second semiconductor layer. The semiconductor layer sequence includes a recess, which extends from a major face of the semiconductor layer sequence facing the carrier through the active region into the first semiconductor layer and is provided for electrical contacting of the first semiconductor layer. The carrier includes a number of switches, which are each provided for controlling at least one pixel.

The invention disclosed a preparation method for a high-voltage LED device integrated with a pattern array, comprising the following process steps: providing a substrate, and forming a N-type GaN limiting layer, an epitaxial light-emitting layer and a P-type GaN limiting layer on the substrate in sequence; isolating the N-GaN limiting layer, the epitaxial light-emitting layer and the P-GaN limiting layer on the substrate into at least two or more independent pattern units by means of photo lithography and etching process, wherein each of the pattern unit is in a triangular shape, and very two adjacent pattern units are arranged in an opposing and crossed manner to form a quadrangle, and the quadrangles formed by a plurality of adjacent pattern units are distributed in array; and connecting each pattern unit with metal wires to form a series connection and/or a parallel connection, thereby forming a plurality of interconnected LED chips. For the purpose of improving the current distribution so as to increase the luminescent efficiency of the device, a current blocking layer is also arranged beneath the P-type metal contact of each unit in addition, an insulation material is also arranged to cover the surface of the chip so as to achieve the purposes of protecting the chip and increasing the light extraction efficiency of the chip.