A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.

After sequentially forming a first multilayer structure comprising a first set of semiconductor layers suitable for formation of a photodetector, an etch stop layer and a second multilayer structure comprising a second set of semiconductor layers suitable for formation of a light source over a substrate, the second multilayer structure is patterned to form a light source in a first region of the substrate. A first trench is then formed extending through the etch stop layer and the first multilayer structure to separate the first multilayer structure into a first part located underneath the light source and a second part that defines a photodetector located in a second region of the substrate. Next, an interlevel dielectric (ILD) layer is formed over the light source, the photodetector and the substrate. A second trench that defines a microfluidic channel is formed within the ILD layer and above the photodetector.

The present invention relates to the growing of nitride semiconductors, applicable for a multitude of semiconductor devices such as diodes, LEDs and transistors. According to the method of the invention nitride semiconductor nanowires are grown utilizing a CVD based selective area growth technique. A nitrogen source and a metal-organic source are present during the nanowire growth step and at least the nitrogen source flow rate is continuous during the nanowire growth step. The V/III-ratio utilized in the inventive method is significantly lower than the V/III-ratios commonly associated with the growth of nitride based semiconductor.

A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).

There are disclosed herein various implementations of a semiconductor component with a multi-layered nucleation body and method for its fabrication. The semiconductor component includes a substrate, a nucleation body situated over the substrate, and a group III-V semiconductor device situated over the nucleation body. The nucleation body includes a bottom layer formed at a low growth temperature, and a top layer formed at a high growth temperature. The nucleation body also includes an intermediate layer that is formed substantially continuously using a varying intermediate growth temperature.

The invention concerns an optoelectronic component comprising a layer structure with a light-active layer. In a first lateral region the light-active layer has a higher density of V-defects than in a second lateral region.

Described herein is a method for manufacturing a stack of semiconductor materials in which a growth substrate is separated from the stack after a semiconductor material, e.g., a Group III nitride semiconductor material, is grown on the substrate. The separation is effected in a spalling procedure in which spalling-facilitating layers are deposited over a protective cap layer that is formed over the Group III-nitride semiconductor material. Such spalling-facilitating layers may include a handle layer, a stressor layer, and an optional adhesion layer. The protective cap layer protects the Group III-nitride from being damaged by the depositing of one or more of the spalling-facilitating layers. After spalling to remove the growth substrate, additional processing steps are taken to provide a semiconductor device that includes undamaged semiconductor material. In one arrangement, the semiconductor material is GaN and includes p-doped GaN region that was undamaged during manufacturing.

A light emitting diode device has a bulk gallium and nitrogen containing substrate with an active region. The device has a lateral dimension and a thick vertical dimension such that the geometric aspect ratio forms a volumetric diode that delivers a nearly uniform current density across the range of the lateral dimension.

The invention relates to a method for manufacturing a semi-conducting material including a layer (50) of nitride of a group 13 element comprising active areas (52) for manufacturing electronic components, and inactive areas (51), the active and inactive areas extending on a front face (53) of the layer of nitride of a group 13 element, the concentration of crystal defects in the active areas being less than the concentration of defects in the inactive areas, the method comprising steps consisting of: using a mask for forming on an initial substrate (10): first regions for growing active areas and second regions (11) for growing inactive areas, the mask comprising a plurality of apertures each defining an active area pattern on the initial substrate, and growing (700) the layer of nitride of group 13 element comprising the active and inactive areas on the first and second regions,
remarkable in that the method further comprises the following steps: receiving a theoretical pattern pitch, the theoretical pattern pitch corresponding to a desired distance between two adjacent active area patterns on the front face of the layer of nitride of group 13 element, calculating at least one mask pitch different from the theoretical pattern pitch for compensating shifts in the active area patterns, the shifts of the active area patterns being due to growth conditions of the semi-conducting material, the mask pitch corresponding to a distance between two adjacent apertures of the protective mask.

Disclosed is a substrate structure and a method for forming the same, in which a high-quality nitride semiconductor layer may be formed with a reduced stress applied to the nitride semiconductor layer at the growth of the nitride semiconductor layer and also be easily separated from the substrate, and a semiconductor lamination structure using the same and a method for forming the same, and a method for manufacturing a nitride semiconductor using the same. The substrate structure includes a single-crystal substrate heterogeneous from a nitride semiconductor, and a crystallized inorganic thin film having a leg portion configured to contact the substrate to define an integrated cavity between the leg portion and the substrate and an upper surface extending from the leg portion and parallel to the substrate, the crystallized inorganic thin film having the same crystal structure as the substrate.