Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (BN) spacer on a gate stack, such as a gate stack of a planar FET or FinFET. The boron nitride spacer is fabricated using atomic layer deposition (ALD) and/or plasma enhanced atomic layer deposition (PEALD) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (Si), silicon germanium (SiGe), germanium (Ge), and/or III-V compounds. Furthermore, the boron nitride spacer may be fabricated to have various desirable properties, including a hexagonal textured structure.

Disclosed examples include microelectronic devices, e.g. integrated circuits, which include a source region and a drain region extending into a semiconductor substrate, the semiconductor substrate having a second conductivity type, the source region and drain region having an opposite first conductivity type. A channel region having the first conductivity type extends between the source region and the drain region. A gate electrode over the channel region has a first portion and a second portion. The first portion has the second conductivity type and a first dopant concentration. The second portion extends from the first portion toward the source region and has the second conductivity type and a second higher dopant concentration. A self-aligned implant is used to simultaneously implant dopants near the source end of the gate electrode and in the semiconductor substrate near the source region.

A semiconductor device is provided. The semiconductor device may include a silicon carbide substrate, a silicon layer formed at a first side of the silicon carbide substrate, a gate oxide layer formed on the silicon layer, a gate terminal formed on the gate oxide layer, a drain terminal formed at a second side of the silicon carbide substrate opposite the first side, and a source terminal formed at the first side of the silicon carbide substrate, and at opposite ends of the silicon layer.

MOSFET-based IC architectures, including SOI NEDMOS ICs and bulk semiconductor LDMOS ICs, that mitigate or eliminate the problems of edge transistors. One IC embodiment includes end-cap body contact regions angle-implanted to have a first characteristic (e.g., P+), a drift region, and a gate structure partially overlying the end-cap body contact regions and the drift region and including a conductive layer having a third characteristic (e.g., N+) and a first side angle-implanted to have the first characteristic. Steps for fabricating such an IC include implanting a dopant at an angle in the range of about 5 to about 60 within the end-cap body contact regions and within the first side of the conductive layer in a region of the gate structure overlying the end-cap body contact regions, wherein the angle-implanted dopant results in the first characteristic for the end-cap body contact regions and the first side of the conductive layer.

Integrated circuit structures having patch spacers, and methods of fabricating integrated circuit structures having patch spacers, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. An internal gate spacer is between vertically adjacent ones of the stack of horizontal nanowires and laterally adjacent to the gate structure. An external gate spacer is along sides of the gate structure and over the stack of horizontal nanowires, the external gate spacer having one or more patch spacers therein.

Disclosed are methods and systems for providing silicon carbide films. A layer of silicon carbide can be provided under process conditions that employ one or more silicon-containing precursors that have one or more silicon-hydrogen bonds and/or silicon-silicon bonds. The silicon-containing precursors may also have one or more silicon-oxygen bonds and/or silicon-carbon bonds. One or more radical species in a substantially low energy state can react with the silicon-containing precursors to form the silicon carbide film. The one or more radical species can be formed in a remote plasma source.

A first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. The first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. The second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. A source/drain trench is formed in a region of the stack to expose side surfaces of the layers. A first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. A spacer is formed in the gap. A source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.

A high-voltage MOS transistor includes a semiconductor substrate, a plurality of active regions, a gate insulation layer, and a gate electrode. The active regions are defined by an isolation structure, wherein the active regions include a channel portion and two side portions, the channel portion has first opposite sides and second opposite sides, and the two side portions are at the first opposite sides of the channel portion. The gate insulation layer is disposed on a surface of the channel portion. The gate electrode is disposed on the gate insulation layer and extending on a portion of the isolation structure, wherein the gate electrode includes a pair of channel edge openings and a plurality of slits. The pair of channel edge openings are at the second opposite sides of the channel portion to expose a portion of the gate insulation layer, and the slits are disposed over the channel portion.

The present disclosure generally relates to a semiconductor device having a reduced height gate electrode layer. In an example, a semiconductor device includes a substrate, a gate dielectric layer, a gate electrode layer, a doped source/drain region, and a dielectric layer. The gate dielectric layer is on a surface of the substrate. The gate electrode layer is on the gate dielectric layer. The doped source/drain region is in the substrate and has a metallurgical junction parallel to a plane coplanar with the surface of the substrate. The metallurgical junction extends to a first vertical distance from the surface of the substrate. The gate electrode layer has a top surface that is a second vertical distance away from the surface of the substrate. The second vertical distance is equal to or less than half of the first vertical distance. The dielectric layer is over the substrate and the gate electrode layer.

A method for fabricating a semiconductor device is disclosed. The method includes forming a first interlayer insulating layer including a first trench that is defined by a first gate spacer and a second trench that is defined by a second gate spacer on a substrate, forming a first gate electrode that fills a part of the first trench and a second gate electrode that fills a part of the second trench, forming a first capping pattern that fills the remainder of the first trench on the first gate electrode, forming a second capping pattern that fills the remainder of the second trench on the second gate electrode, forming a second interlayer insulating layer that covers the first gate spacer and the second gate spacer on the first interlayer insulating layer, forming a third interlayer insulating layer on the second interlayer insulating layer and forming a contact hole that penetrates the third interlayer insulating layer and the second interlayer insulating layer between the first gate electrode and the second gate electrode.