Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

A field effect transistor (FET) configuration is provided having a gate region with a split work function for the source-side and drain-side of the gate region. The work function of a material is defined as the minimum energy required to extract an electron from the surface of the material to free space. Accordingly, the source-side portion of the gate region has a first work function that less than a second work function of the drain-side portion, the result of which is increased breakdown voltage at the drain-gate interface, without significantly increasing the threshold voltage of the FET. The split work function is achieved by layering n-type gate material over p-type gate material in the drain-side portion of the gate region, while only the n-type gate material us used in the source-side portion of the gate region.

Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.

A flash memory disposed on a substrate is provided. The flash memory includes a semiconductor transistor including stacked gate structures, lightly doped regions and spacers. The stacked gate structures include a gate dielectric layer, a first conductive layer, a dielectric layer and a second conductive layer sequentially disposed on the substrate. The dielectric layer has an opening there around such that the first conductive layer electrically connects with the second conductive layer. The lightly doped regions are disposed in the substrate under the opening at sides of the stacked gate structures. The spacers are disposed on sidewalls of the stacked gate structures. A width of spacers is adjusted by controlling a height of the first conductive layer under the opening. The lightly doped regions are disposed by using the dielectric layer as a mask layer, so as to gain margins of the lightly doped regions for good electrical properties.

Self-aligned gate endcap (SAGE) architectures with reduced or removed caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with reduced or removed caps, are described. In an example, an integrated circuit structure includes a first gate electrode over a first semiconductor fin. A second gate electrode is over a second semiconductor fin. A gate endcap isolation structure is between the first gate electrode and the second gate electrode, the gate endcap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall. A local interconnect is on the first gate electrode, on the higher-k dielectric cap layer, and on the second gate electrode, the local interconnect having a bottommost surface above an uppermost surface of the higher-k dielectric cap layer.

A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.

A doped or undoped silicon carbide film can be deposited using a remote plasma chemical vapor deposition (CVD) technique. One or more silicon-containing precursors are provided to a reaction chamber. Radical species, such as hydrogen radical species, are provided in a substantially low energy state or ground state and interact with the one or more silicon-containing precursors to deposit the silicon carbide film. A co-reactant may be flowed with the one or more silicon-containing precursors, where the co-reactant is a carbon-containing precursor and each silicon-containing precursor is a silane-based precursor with at least a silicon atom having two or more hydrogen atoms bonded to the silicon atom.

The present disclosure relates to semiconductor structures and, more particularly, to a laterally diffused metal-oxide semiconductor with one or more gate contacts and methods of manufacture. The structure includes: sidewall spacers over a semiconductor substrate; and a gate structure within a space defined by the sidewall spacers. The gate structure includes: a plurality of gate materials over the semiconductor substrate and between the sidewall spacers; and a gate electrode over the plurality of gate materials and contacting the sidewall spacers.