A semiconductor device includes a substrate, a gate stack over the substrate and a gate spacer on a sidewall of the gate stack. The gate spacer includes an outer spacer and an inner spacer between the gate stack and the outer spacer. The outer spacer and the inner spacer have same k-value reduction impurities, and a concentration of the k-value reduction impurities in the inner spacer is greater than a concentration of the k-value reduction impurities in the outer spacer.

A method disclosed herein includes providing a structure. The structure includes a channel layer, a dummy gate structure disposed over the channel layer, and a source/drain feature connected to the channel layer. In a top view the channel layer and the source/drain feature are arranged along a first direction, and in the top view the dummy gate structure extends lengthwise along a second direction different from the first direction. The method further includes forming a silicide layer on the source/drain feature, after forming the silicide layer, replacing the dummy gate structure with a metal gate structure, forming an interlayer dielectric (ILD) layer over the silicide layer, forming a trench in the ILD layer to expose at least a portion of the silicide layer, and forming a contact feature in the trench.

A semiconductor-on-insulator (SOI) substrate includes a handle substrate, a charge-trapping layer located over the handle substrate and including nitrogen-doped polysilicon, an insulating layer located over the charge-trapping layer, and a semiconductor material layer located over the insulating layer. The nitrogen atoms in the charge-trapping layer suppress grain growth during anneal processes used to form the SOI substrate and during subsequent high temperature processes used to form semiconductor devices on the semiconductor material layer. Reduction in grain growth reduces distortion of the SOI substrate, and facilitates overlay of lithographic patterns during fabrication of the semiconductor devices. The charge-trapping layer suppresses formation of a parasitic surface conduction layer, and reduces capacitive coupling of the semiconductor devices with the handle substrate during high frequency operation such as operations in gigahertz range.

In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

Semiconductor devices and methods of manufacture are presented in which spacers are manufactured on sidewalls of gates for semiconductor devices. In embodiments the spacers comprise a first seal, a second seal, and a contact etch stop layer, in which the first seal comprises a first shell along with a first bulk material, the second seal comprises a second shell along with a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a gate structure positioned on the substrate; an inner spacer layer positioned on the substrate and covering the gate structure; and a plurality of antiferroelectric spacer layers positioned on sides of the inner spacer layer with the gate structure in between and positioned on the substrate.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a gate structure positioned on the substrate; an inner spacer layer positioned on the substrate and covering the gate structure; and a plurality of antiferroelectric spacer layers positioned on sides of the inner spacer layer with the gate structure in between and positioned on the substrate.

A trench type silicon carbide MOSFET structure and a preparation method thereof. The trench type silicon carbide MOSFET structure comprises a trench gate region. The trench gate region comprises at least one first PN junction formed by doping; and at least one second PN junction formed by doping, wherein the second PN junction is juxtaposed and oppositely disposed to the first PN junction. The trench type silicon carbide MOSFET structure of the present invention reduces the input capacitance and the output capacitance of the silicon carbide MOSFET structure by forming two PN junctions disposed oppositely.

The present disclosure describes semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate and a gate structure over the substrate, where the gate structure can include two opposing spacers, a dielectric layer formed on side surfaces of the two opposing spacers, and a gate metal stack formed over the dielectric layer. A top surface of the gate metal stack can be below a top surface of the dielectric layer. An example benefit of the semiconductor structure is to improve structure integrity of tight-pitch transistors in integrated circuits.

A semiconductor device includes an active region spanning along a first direction. The semiconductor device includes a first elongated gate spanning along a second direction substantially perpendicular to the first direction. The first elongated gate includes a first portion that is disposed over the active region and a second portion that is not disposed over the active region. The first portion and the second portion include different materials. The semiconductor device includes a second elongated gate spanning along the second direction and separated from the first elongated gate in the first direction. The second elongated gate includes a third portion that is disposed over the active region and a fourth portion that is not disposed over the active region. The third portion and the fourth portion include different materials.