At a front surface of a silicon carbide base, an n.sup.-type drift layer, a p-type base layer, a first n.sup.+-type source region, a second n.sup.+-type source region, and a trench that penetrates the first and the second n.sup.+-type source regions and the p-type base layer and reaches the n-type region are provided. In the trench, the gate electrode is provided via a gate insulating film, an interlayer insulating film is provided in the trench on the gate electrode.

Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

A cell structure of a silicon carbide MOSFET device, comprising a drift region (3) located on a substrate layer (2), a second conducting type well region (4) and a first JFET region (51) that are located in the drift region (3), an enhancement region located within a surface of the well region (4), a gate insulating layer (8) located on a first conducting type enhancement region (6), the well region (4) and the first JFET region (51) and being in contact therewith at the same time, a gate (9) located on the gate insulating layer, source metal (10) located on the enhancement region, Schottky metal (11) located on a second conducting type enhancement region (7) and the drift region (3), a second JFET region (52) located on a surface of the drift region (3) between the Schottky metals (11), and drain metal (12).

In a semiconductor device, a source region is made of an epitaxial layer so as to reduce variation in thickness of a base region and variation in a threshold value. Outside of a cell part, a side surface of a gate trench is inclined relative to a normal direction to a main surface of a substrate, as compared with a side surface of a gate trench in the cell part that is provided by the epitaxial layer of the source region being in contact with the base region.

A field effect transistor includes first section and second sections. The first section includes a drift layer. A first P-well is disposed over the drift layer. A first N-source is disposed over the first P-well. A first channel is disposed in an upper portion of the first P-well. The second section includes an area P-well disposed within the drift layer and formed integral with the first P-well. The area P-well includes sidewalls that extend upwards from the drift layer to form an enclosed structure with an outer perimeter and an inner perimeter. An area N-source surrounds the outer perimeter and is formed integral with the first N-source. An upwardly extending intermediate portion of the drift layer extends upwards though the inner perimeter. A second channel is disposed in an upper portion of the sidewalls and is bounded by the inner perimeter and outer perimeter of the sidewalls.

A semiconductor wafer processing system for processing a semiconductor wafer is presented. The semiconductor wafer processing system comprises: a trench production apparatus configured to produce trenches in the semiconductor wafer, the trenches being arranged next to each other along a first lateral direction (X); a trench filling apparatus configured to epitaxially fill the trenches with a doped semiconductor material; and a controller operatively coupled to at least one of the trench production apparatus and the trench filling apparatus, wherein the controller is configured to control at least one of the trench production apparatus and the trench filling apparatus in dependence of a parameter, the parameter being indicative of at least one of a variation of dopant concentrations of the doped semiconductor material along the first lateral direction (X) that is to be expected when carrying out the epitaxially filling and a deviation of an expected average of the dopant concentrations from a predetermined nominal value.

In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.

A method of manufacturing a semiconductor device that includes a junction field effect transistor, the junction field effect transistor including a semiconductor substrate of a first conductivity type, an epitaxial layer of the first conductivity type formed on the semiconductor substrate, a source region of the first conductivity type formed on a surface of the epitaxial layer, a channel region of the first conductivity type formed in a lower layer of the source region, a pair of trenches formed in the epitaxial layer so as to sandwich the source region therebetween, and a pair of gate regions of a second conductivity type, opposite to the first conductivity type, formed below a bottom of the pair of trenches.

A method of manufacturing a semiconductor device includes forming a second SiC layer of a first conductivity type on a first SiC layer by epitaxial growth, forming a first region of a second conductivity type by selectively ion-implanting first impurities of the second conductivity type into the second SiC layer, removing a portion of the first region, forming a third SiC layer of the first conductivity type on the second SiC layer by epitaxial growth, and forming a second region of the second conductivity type on the first region by selectively ion-implanting second impurities of the second conductivity type into the third SiC layer.

A method for manufacturing a semiconductor device includes a step of preparing a SiC substrate, a step of fixing the SiC substrate on an electrostatic chuck and heat-treating the SiC substrate, and a step of performing ion implantation treatment on the SiC substrate fixed on the electrostatic chuck and heat-treated. The step of heat-treating includes an outer circumferential-side chucking step which generates an electrostatic attraction force between an outer circumferential region of the SiC substrate and an outer circumferential portion of the electrostatic chuck, the outer circumferential portion facing the outer circumferential region, and an inner circumferential-side chucking step which is started after the outer circumferential-side chucking step is started, and generates an electrostatic attraction force between an inner circumferential region of the SiC substrate and an inner circumferential portion of the electrostatic chuck, the inner circumferential portion facing the inner circumferential region.