Methods of forming a semiconductor structure include the use of channeled implants into silicon carbide crystals. Some methods include providing a silicon carbide layer having a crystallographic axis, heating the silicon carbide layer to a temperature of about 300 C. or more, implanting dopant ions into the heated silicon carbide layer at an implant angle between a direction of implantation and the crystallographic axis of less than about 2, and annealing the silicon carbide layer at a time-temperature product of less than about 30,000 C.-hours to activate the implanted ions.

A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm.sup.2.

The present disclosure relates to a bipolar junction transistor (BJT) structure that significantly reduces current crowding while improving the current gain relative to conventional BJTs. The BJT includes a collector, a base region, and an emitter. The base region is formed over the collector and includes at least one extrinsic base region and an intrinsic base region that extends above the at least one extrinsic base region to provide a mesa. The emitter is formed over the mesa. The BJT may be formed from various material systems, such as the silicon carbide (SiC) material system. In one embodiment, the emitter is formed over the mesa such that essentially none of the emitter is formed over the extrinsic base regions. Typically, but not necessarily, the intrinsic base region is directly laterally adjacent the at least one extrinsic base region.

An insulated gate semiconductor device provided herein includes a front electrode and a rear electrode and is configured to switch a conducting path between the front electrode and the rear electrode. The insulated gate semiconductor device includes a first circumferential trench provided in the front surface; a second circumferential trend provided in the front surface and deeper than the first circumferential trench; a fifth region of a second conductivity type exposed on a bottom surface of the first circumferential trench; a sixth region of the second conductivity type exposed on a bottom surface of the second circumferential trench; and a seventh region of a first conductivity type connected to the third region and separating the fifth region from the sixth region. A front side end portion of the sixth region being located on a rear side with respect to a rear side end portion of the fifth region.

A semiconductor device of an embodiment includes a SiC layer having a surface, the surface inclined at an angle of 0 to 10 with respect to a {000-1} face or the surface having a normal line direction inclined at an angle of 80 to 90 with respect to a <000-1> direction, a gate electrode, a gate insulating layer provided between the surface and the gate electrode, and a region provided between the surface and the gate insulating layer, a maximum concentration of deuterium (D) in the region being 110.sup.20 cm.sup.3 or more and a maximum concentration of hydrogen (H) in the region being 110.sup.19 cm.sup.3 or less.

A silicon carbide semiconductor device includes a silicon carbide layer having a first main surface and a second main surface opposite to the first main surface. In the second main surface of the silicon carbide layer, a trench having a depth in a direction from the second main surface toward the first main surface is provided, and the trench has a sidewall portion where a second layer and a third layer are exposed and a bottom portion, where a first layer is exposed. A position of the bottom portion of the trench in a direction of depth of the trench is located on a side of the second main surface relative to a site located closest to the first main surface in a region where the second layer and the first layer are in contact with each other, or located as deep as the site in the direction of depth.

A semiconductor device of an embodiment includes a SiC layer having a surface inclined with respect to a {000-1} face at an angle of 0 to 10 or a surface a normal line direction of which is inclined with respect to a <000-1> direction at an angle of 80 to 90, a gate electrode, an insulating layer at least a part of which is provided between the surface and the gate electrode, and a region, at least apart of which is provided between the surface and the insulating layer, including a bond between carbon and carbon.

A trench has first to third side surfaces respectively constituted of first to third semiconductor layers. A first side wall portion included in a first insulating film has first to third regions respectively located on the first to third side surfaces. A second insulating film has a second side wall portion located on the first side wall portion.

The second side wall portion has one end and the other end, the one end being connected to the second bottom portion of the second insulating film, the other end being located on one of the first and second regions, the other end being separated from the third region.

A method for manufacturing a semiconductor device includes carrying out a first heat treatment accompanied by nitration on a first insulating film and a silicon carbide substrate in a first gas atmosphere, after the carrying out of the first heat treatment and after a temperature of the silicon carbide substrate has become 700 C. or less, removing the silicon carbide substrate from a processing apparatus and exposing the silicon carbide substrate to air in an atmosphere outside of the processing apparatus, and after the exposing of the silicon carbide substrate to air in the atmosphere, carrying out a second heat treatment on the first insulating film and the silicon carbide substrate in a second gas atmosphere which is an inert gas.

A silicon carbide vertical MOSFET includes an N-counter layer of a first conductivity type formed in a surface layer other than a second semiconductor layer base layer selectively formed in a low concentration layer on a surface of the substrate, a gate electrode layer formed through a gate insulating film in at least a portion of an exposed portion of a surface of a third semiconductor layer of a second conductivity type between a source region of the first conductivity type and the N-counter layer of the first conductivity type, and a source electrode in contact commonly with surfaces of the source region and the third semiconductor layer. Portions of the second conductivity type semiconductor layer are connected with each other in a region beneath the N-counter layer.