After a trench is formed, a deposition film is formed on the front surface of a base material and an inner wall of the trench such that a thickness of a portion of the deposition film covering the front surface of the base material is greater than a thickness of a portion of the deposition film covering the inner wall of the trench. The total thickness of the deposition film is then reduced until the inner wall of the trench is exposed, leaving only the portion of the deposition film covering the front surface of the base material. By performing sacrificial oxidation in this state, the thermal oxide film caused by thermal oxidation barely grows at the interface of the front surface of the base material and the deposition film, and thus the thickness of an n+ source region is mostly maintained.

A silicon carbide semiconductor switching device having a planar metal oxide semiconductor insulated gate structure. The silicon carbide semiconductor switching device includes a silicon carbide semiconductor substrate having a bandgap wider than that of silicon, a drift layer formed on the silicon carbide semiconductor substrate, a base region selectively formed in the drift layer at a top surface thereof, a source contact region selectively formed in the base region at a top surface thereof, a trench formed in the drift layer at the top surface thereof, the trench having a depth that is shallower than a depth of the source contact region, a gate electrode embedded in the trench, a top surface of the gate electrode being substantially flush with a top surface of the source contact region, and an interlayer insulating film formed on the top surfaces of the source contact region and the gate electrode.

According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.

A method for manufacturing a silicon carbide device includes providing a silicon carbide wafer and manufacturing a mask layer on top of the silicon carbide wafer. Further, the method includes structuring the mask layer at an edge of a silicon carbide device to be manufactured, so that the mask layer includes a bevel at the edge of the silicon carbide device to be manufactured. Additionally, the method includes etching the mask layer and the silicon carbide wafer by a mutual etching process, so that the bevel of the mask layer is reproduced at the edge of the silicon carbide device.

The silicon carbide semiconductor layer includes a first impurity region, a second impurity region, and a third impurity region. Turning to a first position at which an impurity concentration 1/10 as high as a highest impurity concentration is exhibited in a concentration profile of an impurity having the first conductivity type in a direction perpendicular to the main surface in the third impurity region and a second position at which an impurity concentration 1/10 as high as a highest impurity concentration is exhibited in a concentration profile of an impurity having the second conductivity type in the direction perpendicular to the main surface in the second impurity region, a first depth from the main surface to the first position is shallower than a second depth from the main surface to the second position. The electrode is electrically connected to the second impurity region and the third impurity region.

An insulating layer is formed on a substrate made of silicon carbide. By performing etching using a mask layer formed on the insulating layer, a contact hole is formed in the insulating layer to expose a contact region, which is a portion of a main surface of the substrate. The step of forming the contact hole includes a step of providing the contact region with a surface roughness Ra of not less than 0.5 nm. An electrode layer is formed in contact with the contact region. By heating the electrode layer and the substrate, siliciding reaction is caused between the electrode layer and the contact region.

A method of manufacturing a silicon carbide ingot includes the steps of: preparing a silicon carbide seed substrate having a first main surface and a second main surface located opposite the first main surface; forming a metal carbide film on the second main surface at a temperature of not more than 2000 C.; and growing a silicon carbide single crystal on the first main surface by sublimation, while supporting the silicon carbide seed substrate having the metal carbide film formed thereon by a supporting member. In the growing step, a supported portion of the surface of the silicon carbide seed substrate supported by the supporting member is in a region other than a region where the metal carbide film has been formed.

A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure including a gate insulating film contacting the silicon carbide semiconductor structure and a gate electrode formed on the gate insulating film, an interlayer insulating film covering the insulated gate structure, a metal layer provided on the interlayer insulating film for absorbing or blocking hydrogen, and a main electrode provided on the metal layer and electrically connected to the silicon carbide semiconductor structure.

A semiconductor device of trench gate type is provided that has achieved both large on-current and high off-state breakdown voltage. Around trench T and between it and electric field relaxation p-layer 16, low resistance n-layer 17 is provided. Low resistance n-layer 17 is formed deeper than trench T, and shallower than electric field relaxation p-layer 16, being connected to n.sup.-layer (drift layer) 12 just thereunder, and thus low resistance n-layer 17 and n.sup.-layer 12 are integrated to form a drift layer. Although low resistance n-layer 17 is n-type as is n.sup.-layer 12, donor concentration thereof is set higher than that of n.sup.-layer 12, thereby low resistance n-layer 17 having a resistivity lower than that of n.sup.-layer 12. This low resistance n-layer 17 is provided in on-current path (between electric field relaxation p-layer 16 and trench T), whereby low resistance n-layer 17 can lower the resistance to on-current.

A semiconductor device of the present invention is a semiconductor device having a semiconductor layer comprising a wide band gap semiconductor, wherein the semiconductor layer includes: a first conductivity-type source region, a second conductivity-type channel region and a first conductivity-type drain region, which are formed in this order from the surface side of the semiconductor layer; a source trench lying from the surface of the semiconductor layer through the source region and the channel region to the drain region; a gate insulating film formed so as to contact the channel region; a gate electrode facing the channel region with the gate insulating film interposed therebetween; and a first breakdown voltage holding region of a second conductivity type formed selectively on the side face or the bottom face of the source trench, and the semiconductor device includes a barrier formation layer, which is joined with the drain region in the source trench, for forming, by junction with the drain region, a junction barrier lower than a diffusion potential of a body diode formed by p-n junction between the channel region and the drain region.