A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure mainly includes a stress control layer disposed between a light emitting layer and a p-type carrier blocking layer. The p-type carrier blocking layer is made from Al.sub.xGa.sub.1-xN (0<x<1) while the stress control layer is made from Al.sub.xIn.sub.yGa.sub.1-x-yN (0<x<1, 0<y<1, 0<x+y<1). The light emitting layer has a multiple quantum well structure formed by a plurality of well layers and barrier layers stacked alternately. There is one well layer disposed between the two barrier layers. Thereby the stress control layer not only improves crystal quality degradation caused by lattice mismatch between the p-type carrier blocking layer and the light emitting layer but also reduces effects of compressive stress on the well layer caused by material differences.

An optoelectronic component includes a layer structure which has a first gallium nitride layer and an aluminum-containing nitride intermediate layer. In this case, the aluminum-containing nitride intermediate layer adjoins the first gallium nitride layer. The layer structure has an undoped second gallium nitride layer which adjoins the aluminum-containing nitride intermediate layer.

A superlattice and method for forming that superlattice are disclosed. In particular, an engineered layered single crystal structure forming a superlattice is disclosed. The superlattice provides p-type or n-type conductivity, and comprises alternating host layers and impurity layers, wherein: the host layers consist essentially of a semiconductor material; and the impurity layers consist essentially of a corresponding donor or acceptor material.

An LED driving apparatus according to an exemplary embodiment of the present inventive concept may include a rectifier circuit rectifying alternating current (AC) power to generate driving power for operating a plurality of LED arrays; a controller integrated circuit (IC) including a plurality of internal switches connected to respective output terminals of the plurality of LED arrays and controlling a path of a current flowing in the plurality of LED arrays by adjusting operations of the plurality of internal switches according to a magnitude of the driving power; and a current controlling circuit connected to the output terminal of at least one of the plurality of LED arrays and controlling a current flowing in the at least one LED array.

The electronic device comprises a substrate (1), at least one semiconductor nanowire (2) and a buffer layer (3) interposed between the substrate (1) and said nanowire (2). The buffer layer (3) is at least partly formed by a transition metal nitride layer (9) from which extends the nanowire (2), said transition metal nitride being chosen from: vanadium nitride, chromium nitride, zirconium nitride, niobium nitride, molybdenum nitride, hafnium nitride or tantalum nitride.

A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

A hetero-substrate, a nitride-based semiconductor light emitting device, and a method of manufacturing the same are provided. The hetero-substrate may include a substrate including a silicon semiconductor, a buffer layer disposed on the substrate, a first semiconductor layer disposed on the buffer layer and including a nitride semiconductor, a second semiconductor layer disposed on the first semiconductor layer and including a first conductive type nitride semiconductor having a first doping concentration, and a stress control structure disposed between the first semiconductor layer and the second semiconductor layer and including at least one stress compensation layer and at least one third semiconductor layer including a first conductive type nitride semiconductor having a second doping concentration that is the same or lower than the first doping concentration.

A heteroepitaxy strain-management structure for a light emitting device includes: a substrate or template; an epitaxial layer to be epitaxially formed over the substrate or template, wherein a calculated in-plane compressive strain to be exerted by the substrate or template to the epitaxial layer is equal to or larger than 1%; and a heavily doped interlayer inserted in-between the epitaxial layer and the substrate or template; wherein the heavily doped interlayer is of substantially the same material composition as that of the epitaxial layer, with a thickness of 40-400 nm, and doped at a doping level in the range of 510.sup.19 to 510.sup.20 cm.sup.3. Also provided is an ultraviolet light emitting device having a heteroepitaxy strain-management structure.

Bulk single crystals of AlN having a diameter greater than about 25 mm and dislocation densities of about 10,000 cm.sup.2 or less and high-quality AlN substrates having surfaces of any desired crystallographic orientation fabricated from these bulk crystals.

Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.