The present invention provides an array substrate, a method of fabricating the array substrate, and a display device. The method of fabricating the array substrate of the present invention comprises steps of: sequentially forming a first transparent conductive film and a source-drain metal film on a substrate; forming a source-drain metal pattern by performing a patterning process on the source-drain metal film; forming a pattern comprising a pixel electrode and a compensation structure that is provided below the source-drain metal pattern by performing a patterning process on the first transparent conductive film.

An Al wiring film having a tapered shape is obtained easily and in a stable manner. An Al wiring film has a double-layer structure including a first Al alloy layer made of Al or an Al alloy, and a second Al alloy layer laid on the first Al alloy layer and having a composition different from a composition of the first Al alloy layer by containing at least one element of Ni, Pd, and Pt. The second Al alloy layer is etched by an alkaline chemical solution used in a developing process of a photoresist, and an end portion of the second Al alloy layer recedes from an end portion of the photoresist. Thereafter, by performing wet etching using the photoresist as a mask, a cross section of the Al wiring film becomes a tapered shape.

A manufacturing method includes forming a gate member and a common electrode line on a substrate. A gate insulating layer is formed on the gate member and the common electrode line. A semiconductor member and a data member are formed on the gate insulating layer. A first passivation layer is formed on the semiconductor member and the data member. A plurality of color filters is formed on the first passivation layer. A conductor layer and a second passivation layer are formed on the plurality of color filters. A first contact hole exposes a common electrode. A second contact hole exposes the drain electrode. The first and second contact holes are formed by a photolithography process. A pixel electrode connected to the drain electrode is formed through the first contact hole. A connecting member connected to the common electrode line and the common electrode is formed through the second contact hole.

It is an object of the present invention to prevent an insulating film from peeling in a section where the insulating film is adjacent to a sealing region. Over a first substrate 104, a pixel portion 100 provided with a light emitting element, a source driver 101, a gate driver 102, and a sealing region 103 are provided. A light emitting element is sealed between the first substrate 104 and a second substrate 110 by a sealant 108. An insulating film 107 serves as a partition wall of the light emitting element. An end portion of the insulating film 107 which is adjacent to the sealing region 103 does not overlap with a step formed by a side surface and an upper surface of a conductive film 106 which serves as a wiring.

An object is to reduce parasitic capacitance of a signal line included in a liquid crystal display device. A transistor including an oxide semiconductor layer is used as a transistor provided in each pixel. Note that the oxide semiconductor layer is an oxide semiconductor layer which is highly purified by thoroughly removing impurities (hydrogen, water, or the like) which become electron suppliers (donors). Thus, the amount of leakage current (off-state current) can be reduced when the transistor is off. Therefore, a voltage applied to a liquid crystal element can be held without providing a capacitor in each pixel. In addition, a capacitor wiring extending to a pixel portion of the liquid crystal display device can be eliminated. Therefore, parasitic capacitance in a region where the signal line and the capacitor wiring intersect with each other can be eliminated.

The present disclosure provides an electrically conductive structure and a manufacturing method thereof, an array substrate, and a display device. The manufacturing method of the electrically conductive structure including: forming stacked layers of electrically conductive films on a substrate; performing patterning process to the layers of electrically conductive films to form an electrically conductive structure with a preset pattern, an edge of the electrically conductive structure being a step-shaped structure.

A thin-film transistor (TFT) switch includes a gate, a drain, a source, a semiconductor layer, and a fourth electrode. The drain is connected to a first signal. The gate is connected to a control signal to control the switch on or off. The source outputs the first signal when the switch turns on. The fourth electrode and the gate are respectively located at two sides of the semiconductor layer. The fourth electrode is conductive and is selectively coupled to different voltage levels, thereby reducing leakage current in a channel to improve switch characteristic when the switch turns off.

An electronic device of the technology includes: a plurality of first wiring patterns that are electrically coupled to each other partially, and each extend in a first direction; an organic insulating layer that is provided on the first wiring patterns; and a second wiring pattern that is provided on the organic insulating layer.

A flexible display device including a substrate having an active region in which an input image is implemented and a bezel region outside the active region; a signal line (or an electrode) extending from the bezel region and transmitting a signal (or a voltage) to the active region; and a first bypass line provided above or below the signal line with one or more insulating layers interposed therebetween in the bezel region, wherein the first bypass line is connected to the signal line via a first bypass contact hole penetrating through the one or more insulating layers and receives the same signal as that of the signal line, and wherein the first bypass contact hole is provided as at least two bypass contact holes.

An array substrate and a method of manufacturing the same, a display panel and a display device are disclosed. The array substrate includes: a base substrate, and a first conductive layer, a first insulation layer, a semiconductor layer, a second conductive layer, a second insulation layer, and a third conductive layer that are sequentially formed on the base substrate. The first conductive layer includes a gate electrode pattern, the semiconductor layer includes an active area pattern, and the second conductive layer includes a source-drain electrode pattern; the second insulation layer is provided with a connection via hole between the third conductive layer and the second conductive layer; and the semiconductor layer further includes a spacing pad pattern in a region where the connection via hole is provided.