Some embodiments include an integrated assembly having first and second pillars of semiconductor material. The first pillar includes a first source/drain region, and the second pillar includes a second source/drain region. First and second bottom electrodes are coupled with the first and second source/drain regions, respectively. The first and second source/drain regions are spaced from one another by an intervening region. First and second leaker-device-structures extend into the intervening region from the first and second bottom electrodes, respectively. Top-electrode-material extends into the intervening region and contacts the first and second leaker-device-structures. Ferroelectric-insulative-material is between the top-electrode-material and the bottom electrodes. Some embodiments include methods of forming integrated assemblies.

A method for forming a semiconductor device comprises: forming a ferroelectric tunnel junction (FTJ), wherein forming the ferroelectric tunnel junction comprises: forming a first nitrogen-containing electrode on a substrate, the first nitrogen-containing electrode characterized by a first nitrogen percentage; forming a ferroelectric layer over the first nitrogen-containing electrode, the ferroelectric layer comprising a ferroelectric material; and forming a second nitrogen-containing electrode over the ferroelectric layer, the second nitrogen-containing electrode characterized by a second nitrogen percentage. When the first nitrogen percentage is less than the second nitrogen percentage, the method further comprises forming a first interfacial layer between the first nitrogen-containing electrode and the ferroelectric layer. When the first nitrogen percentage is greater than the second nitrogen percentage, the method further comprises forming a second interfacial layer between the ferroelectric layer and the second nitrogen-containing electrode.

A semiconductor package includes a package substrate, an interposer die on the package substrate, the interposer die including a redistribution structure, the redistribution structure including an insulating layer including an organic material, and redistribution layers in the insulating layer, a passive element in the interposer die, where the passive element is electrically connected to the redistribution layers, the passive element including a first electrode, a dielectric film on the first electrode, and a second electrode on the dielectric film, and semiconductor chips on an upper surface of the insulating layer and spaced apart from each other in a horizontal direction on the interposer die, where the semiconductor chips are electrically connected to the package substrate through the redistribution layers. A thickness of the passive element is about 50 m or less, and at least a portion of the dielectric film of the passive element has a crystalline structure.

A device structure according to the present disclosure includes a conductive feature disposed in a first dielectric layer, a ferroelectric tunnel junction (FTJ) stack disposed over the conductive feature, a spacer disposed along sidewalls of the FTJ stack, a second dielectric layer disposed over the spacer and the FTJ stack, and a contact via extending through the second dielectric layer. The FTJ stack includes a bottom electrode layer electrically coupled to the conductive feature, a ferroelectric layer over the bottom electrode layer, and a top electrode layer on the ferroelectric layer. The top electrode layer is formed of a conductive metal oxide.

The present disclosure describes a semiconductor device having a ferroelectric memory with improved retention after cycling (RAC) memory window (MW) performance. The semiconductor device includes an interconnect structure on a substrate, a first electrode on the interconnect structure, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer. The first electrode includes a metal nitride conductive material having a nitrogen concentration greater than a metal concentration. The ferroelectric layer includes a ferroelectric material. The second electrode includes the metal nitride conductive material.

Various aspects relate to a memory cell including: a thermally insulating layer disposed over one or more metallization layers of a metallization; an embedding structure disposed over the thermally insulating layer; and a spontaneously polarizable capacitor structure disposed at least partially within the embedding structure, wherein the spontaneously polarizable capacitor structure includes a spontaneously polarizable memory element; wherein the thermally insulating layer is configured as a heat barrier to reduce a heat transfer through the embedding structure into the one or more metallization layers.

A semiconductor device includes a substrate, lower electrodes on the substrate, a dielectric layer covering the lower electrodes, and an upper electrode covering the dielectric layer. The dielectric layer includes a first region in contact with the lower electrodes, a second region in contact with the upper electrode, and a third region between the first and second regions. The third region includes a first insertion layer including a first oxide including a first metal having a first valence and a second oxide including a second metal having a second valence different from the first valence. A thickness of the dielectric layer is about 40 to about 60 . A thickness of the first insertion layer is about 3 to about 10 . A ratio of the second metal to total elements in the dielectric layer is about 5 at % to about 15 at %.

Some embodiments include an integrated assembly having pillars arranged in an array. The pillars have channel regions between upper and lower source/drain regions. Gating structures are proximate to the channel regions and extend along a row direction. Digit lines are beneath the pillars, extend along a column direction, and are coupled with the lower source/drain regions. Linear structures are above the pillars and extend along the column direction. Bottom electrodes are coupled with the upper source/drain regions. The bottom electrodes have horizontal segments adjacent the upper source/drain regions and have vertical segments extending upwardly from the horizontal segments. The vertical segments are adjacent to lateral sides of the linear structures. Ferroelectric-insulative-material and top-electrode-material are over the bottom electrodes. A slit passes through the top-electrode-material, is directly over one of the linear structures, and extends along the column direction.

Various embodiments of the present disclosure are directed towards a memory cell comprising a blocking layer configured to block diffusion of metal from an electrode of the memory cell to a ferroelectric layer of the memory cell. More particularly, the blocking layer and the ferroelectric layer are between a top electrode of the memory cell and a bottom electrode of the memory cell, which both comprise metal. Further, the blocking layer is between the ferroelectric layer and the electrode, which corresponds to one of the top and bottom electrodes. In some embodiments, the metal of the one of the top and bottom electrodes has a lowest electronegativity amongst the metals of top and bottom electrodes and is hence the most reactive and likely to diffuse amongst the metals of top and bottom electrodes.

A ferroelectric device (100) that includes a metal nitride film (130) with favorable ferroelectricity is provided. The ferroelectric device comprises a first conductor (110), a metal nitride film over the first conductor, a second conductor (120) over the metal nitride film, a first insulator (155) over the second conductor, and a second insulator (152) over the first insulator. The first insulator includes regions in contact with the side surface of the metal nitride film and the side surface and the top surface of the second conductor; the metal nitride film has ferroelectricity; the metal nitride film contains a first element, a second element, and nitrogen; the first element is one or more elements selected from Group 13 elements; the second element is one or more elements selected from Group 2 elements to Group 6 elements and Group 13 elements other than the first element; the first conductor and the second conductor each contain nitrogen; the first insulator contains aluminum and oxygen; and the second insulator contains silicon and nitrogen.