Embodiments of the disclosure generally relate to a hybrid plasma processing system incorporating a remote plasma source (RPS) unit with a capacitively coupled plasma (CCP) unit for substrate processing. In one embodiment, the hybrid plasma processing system includes a CCP unit, comprising a lid having one or more through holes, and an ion suppression element, wherein the lid and the ion suppression element define a plasma excitation region, a RPS unit coupled to the CCP unit, and a gas distribution plate disposed between the ion suppression element and a substrate support, wherein the gas distribution plate and the substrate support defines a substrate processing region. In cases where process requires higher power, both CCP and RPS units may be used to generate plasma excited species so that some power burden is shifted from the CCP unit to the RPS unit, which allows the CCP unit to operate at lower power.

A method of fabricating a pixel array includes forming a transistor network along a frontside of a semiconductor substrate. A contact element is formed for every pixel in the pixel array that is electrically coupled to a transistor within the transistor network. An interconnect layer is formed upon the frontside to control the transistor network with a dielectric that covers the contact element. A cavity is formed in the interconnect layer. A conductive layer is formed along cavity walls of the cavity and a dielectric layer is formed over the conductive layer within the cavity. A photosensitive semiconductor material is deposited over the dielectric layer within the cavity. An electrode cavity is formed that extends into the contact element. The electrode cavity is at least partially filled with a conductive material to form an electrode. The electrode, the conductive layer, and the photosensitive semiconductor material form a photosensitive capacitor.

The invention deals with multi-states nonvolatile opto-ferroelectric memory element and method of preparing the same thereof. This invention describes multi-states nonvolatile opto-ferroelectric memory element consisting of opto-ferroelectric memory material comprised of Pb.sub.1-x(Bi.sub.0.5Li.sub.0.5).sub.x(Ti.sub.1-yZr.sub.y)O.sub.3, wherein x=0.2 to 0.8 and y=0.2 to 0.6, said memory material (PBLZT) phtotovoltaic ferroelectric material is characterized by a single-phase opto-ferroelectric materials, photovoltaic and multi-states ferroelectric memory material. The invention relates to process of preparing multi-states nonvolatile opto-ferroelectric memory material by solid route, solution-gel process and pulsed laser process. It describes development of multi-states nonvolatile opto-ferroelectric memory material at room temperature. Invention describes a ferroelectric material whose polarization is switched by white light and low power LASER (10-50 mW) with wavelength (405 nm).

A method can include applying a patterned mask over a semiconductor structure, the semiconductor structure having a dielectric layer, forming using the patterned mask a material formation trench intermediate first and second spaced apart metal formations formed in the dielectric layer, and disposing a dielectric material formation in the material formation trench.

A variable capacitance device that includes a semiconductor substrate, a redistribution layer disposed on a surface of the semiconductor substrate, and a plurality of terminal electrodes including first and second input/output terminals, a ground terminal and a control voltage application terminal. Moreover, a variable capacitance element section is formed in the redistribution layer from a pair of capacitor electrodes connected to the first and second input/output terminals, respectively, and a ferroelectric thin film disposed between the capacitor electrodes. Further, an ESD protection element is connected between the one of the input/output terminals and the ground terminal is formed on the surface of the semiconductor substrate.

Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.

A semiconductor storage device includes an insulating layer. A ferroelectric capacitor is on the insulating layer and includes a lower electrode, a ferroelectric film, and an upper electrode. An interlayer insulating film is formed on the insulating layer, and has an opening where the ferroelectric capacitor is disposed. A first metal plug is formed in the insulating layer and connected to the lower electrode via the opening. A second metal plug is embedded in the insulating layer outside the ferroelectric capacitor. A hydrogen barrier film covers the ferroelectric capacitor and the interlayer insulating film. An upper surface of the interlayer insulating film is higher than an upper surface of the first metal plug so that a step is therebetween. The lower electrode is formed on the upper surface of the interlayer insulating film, the upper surface of the first metal plug and the step. The upper surface of the interlayer insulating film and the upper surface of the first metal plug are interlinked via a recessed portion of the interlayer insulating film.

A method of manufacturing a semiconductor device includes: forming a conductive film over a semiconductor substrate; forming a first ferroelectric film over the conductive film; forming an amorphous second ferroelectric film over the first ferroelectric film; forming a transition metal oxide material film containing ruthenium over the second ferroelectric film; forming a first conductive metal oxide film over the transition metal oxide material film without exposing the transition metal oxide material film to the air; annealing and crystallizing the second ferroelectric film; and patterning the first conductive metal oxide film, the first ferroelectric film, the second ferroelectric film, and the conductive film to form a ferroelectric capacitor.

This disclosure provides a negative capacitance gate stack structure with a variable positive capacitor to implement a hysteresis free negative capacitance field effect transistors (NCFETs) with improved voltage gain. The gate stack structure provides an effective ferroelectric negative capacitor by using the combination of a ferroelectric negative capacitor and the variable positive capacitor with semiconductor material (such as polysilicon), resulting in the effective ferroelectric negative capacitor's being varied with an applied gate voltage. Our simulation results show that the NCFET with the variable positive capacitor can achieve not only a non-hysteretic I.sub.D-V.sub.G curve but also a better sub-threshold slope.

A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of at least 110.sup.2 Siemens/cm. The composite stack is used to render the non-ferroelectric metal oxide-comprising insulator material to be ferroelectric. Conductive material is formed over the composite stack and the insulator material. Ferroelectric capacitors and ferroelectric field effect transistors independent of method of manufacture are also disclosed.