Embodiments of the disclosure generally relate to a hybrid plasma processing system incorporating a remote plasma source (RPS) unit with a capacitively coupled plasma (CCP) unit for substrate processing. In one embodiment, the hybrid plasma processing system includes a CCP unit, comprising a lid having one or more through holes, and an ion suppression element, wherein the lid and the ion suppression element define a plasma excitation region, a RPS unit coupled to the CCP unit, and a gas distribution plate disposed between the ion suppression element and a substrate support, wherein the gas distribution plate and the substrate support defines a substrate processing region. In cases where process requires higher power, both CCP and RPS units may be used to generate plasma excited species so that some power burden is shifted from the CCP unit to the RPS unit, which allows the CCP unit to operate at lower power.

A dielectric composition containing a complex oxide represented by the formula of A.sub.B.sub.C.sub.2O.sub.++5 as the main component, wherein A represents Ba, B represents at least one element selected from the group consisting of Ca and Sr, C represents at least one element selected from the group consisting of Ta and Nb, and , and meet the following conditions, i.e., ++=1.000, 0.000<0.375, 0.625<1.000, 0.0000.375.

The output voltage of an MRAM is increased by means of an Fe(001)/MgO(001)/Fe(001) MTJ device, which is formed by microfabrication of a sample prepared as follows: A single-crystalline MgO (001) substrate is prepared. An epitaxial Fe(001) lower electrode (a first electrode) is grown on a MgO(001) seed layer at room temperature, followed by annealing under ultrahigh vacuum. A MgO(001) barrier layer is epitaxially formed on the Fe(001) lower electrode (the first electrode) at room temperature, using a MgO electron-beam evaporation. A Fe(001) upper electrode (a second electrode) is then formed on the MgO(001) barrier layer at room temperature. This is successively followed by the deposition of a Co layer on the Fe(001) upper electrode (the second electrode). The Co layer is provided so as to increase the coercive force of the upper electrode in order to realize an antiparallel magnetization alignment.

A semiconductor storage device includes an insulating layer. A ferroelectric capacitor is on the insulating layer and includes a lower electrode, a ferroelectric film, and an upper electrode. An interlayer insulating film is formed on the insulating layer, and has an opening where the ferroelectric capacitor is disposed. A first metal plug is formed in the insulating layer and connected to the lower electrode via the opening. A second metal plug is embedded in the insulating layer outside the ferroelectric capacitor. A hydrogen barrier film covers the ferroelectric capacitor and the interlayer insulating film. An upper surface of the interlayer insulating film is higher than an upper surface of the first metal plug so that a step is therebetween. The lower electrode is formed on the upper surface of the interlayer insulating film, the upper surface of the first metal plug and the step. The upper surface of the interlayer insulating film and the upper surface of the first metal plug are interlinked via a recessed portion of the interlayer insulating film.

Embodiments provided herein describe methods and systems for forming high-k dielectric materials, as well as devices that utilize such materials. A property of a high-k dielectric material is selected. A value of the selected property of the high-k dielectric material is selected. A chemical composition of the high-k dielectric material is selected from a plurality of chemical compositions of the high-k dielectric material. The selected chemical composition of the high-k dielectric material includes an amount of nitridation associated with the selected value of the selected property of the high-k dielectric material. The high-k dielectric material is formed with the selected chemical composition.

A dielectric-thin-film forming composition for forming a BST dielectric thin film, includes a liquid composition for forming a thin film which takes a form of a mixed composite metal oxide in which a composite oxide B including Cu (copper) is mixed into a composite metal oxide A expressed by a formula: Ba.sub.1-xSr.sub.xTi.sub.yO.sub.3 (wherein 0.2<x<0.6 and 0.9<y<1.1), the liquid composition is an organic metal compound solution in which a raw material for composing the composite metal oxide A and a raw material for composing the composite oxide B are dissolved in an organic solvent at a proportion having a metal atom ratio expressed by the formula shown above and a molar ratio between A and B in the range of 0.001B/A<0.15.

The present invention relates to a method for fabricating an electronic component, comprising fabricating, on a substrate (102) at least one integrated MIM capacitor (114) having a top capacitor electrode (118) and a bottom capacitor electrode (112) at a smaller distance from the substrate than the top capacitor electrode; fabricating an electrically insulating first cover layer (120) on the top capacitor electrode, which first cover layer partly or fully covers the top capacitor electrode and is made of a lead-containing dielectric material; thinning the first cover layer; fabricating an electrically insulating second cover layer (124) on the first cover layer, which second cover layer partly or fully covers the first cover layer and has a dielectric permittivity smaller than that of the first cover layer; and fabricating an electrically conductive resistor layer (126) on the second cover layer, which resistor layer has a defined ohmic resistance.

A method of fabricating a semiconductor device with conductive patterns comprises sequentially forming an etch-target layer and a middle mold layer on a substrate, forming a first upper mold pattern and a second upper mold pattern on the middle mold layer to have top surfaces at different levels, etching the middle mold layer using the first and second upper mold patterns as an etch mask to form first and second middle mold patterns, respectively, forming a third middle mold pattern between the first and second middle mold patterns, and etching the etch-target layer using the first to third middle mold patterns as an etch mask to form conductive patterns.

Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.

Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.