As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

A first insulating layer containing a silicon oxide is disposed on a surface of an insulating member. A transistor is disposed over a part of an area of a first insulating layer. A second insulating layer covers the first insulating layer and the transistor. A first wiring is disposed on the second insulating layer. A through-hole extends through the second insulating layer and the first insulating layer from a lower surface of the first wiring to the insulating member. At least a part of an outer edge of the through-hole overlaps the first wiring in a plan view. The first wiring includes a lower layer that is in contact with the second insulating layer, and the lower layer is formed from Ta, W, a Ta compound, or a W compound.

Ions are implanted into a first wafer through a top side, generating an ion damaged layer underneath the substrate film of the first wafer. A stress inducing layer is applied on a surface on the top side of the first wafer on one of the ion implanted side and the opposite side. The substrate film is separated from the first wafer at the ion damaged layer. the separated substrate film is bonded to a second wafer at a surface on one of a first side and a second side that this opposite of the first side of the second wafer to form an engineered wafer.

Structures and methods are disclosed in which a layer stack can be formed with a plurality of layers of a metal, where each of the layers of metal can be separated by a layer of a dielectric. An opening in the layer stack can be formed such that a semiconductor layer beneath the plurality of layers of the metal is uncovered. One or more vertical channel structures can be formed within the opening by epitaxial growth. The vertical channel structure can include a vertically oriented transistor. The vertical channel structure can include an interface of a silicide metal with a first metal layer of the plurality of metal layers. The interface can correspond to one of a source or a drain connection of a transistor. The silicide metal can be annealed above a temperature threshold to form a silicide interface between the vertical channel structure and the first metal layer.

A method includes forming a gate stack, growing a source/drain region on a side of the gate stack through epitaxy, depositing a contact etch stop layer (CESL) over the source/drain region, depositing an inter-layer dielectric over the CESL, etching the inter-layer dielectric and the CESL to form a contact opening, and etching the source/drain region so that the contact opening extends into the source/drain region. The method further includes depositing a metal layer extending into the contact opening. Horizontal portions, vertical portions, and corner portions of the metal layer have a substantially uniform thickness. An annealing process is performed to react the metal layer with the source/drain region to form a source/drain silicide region. The contact opening is filled to form a source/drain contact plug.

A semiconductor device may include a source on a first side of a gate. The semiconductor device may include a drain on a second side of the gate, where the second side of the gate is opposite to the first side of the gate. The semiconductor device may include a first contact over the source. The semiconductor device may include a second contact over the drain. The semiconductor device may include an air gap over the gate between at least the first contact and the second contact. The semiconductor device may include at least two dielectric materials in each of a region between the air gap and the first contact and a region between the air gap and the second contact.

A crystal that is useful for semiconductor element and a semiconductor element that has enhanced electrical properties are provided. A crystal, including: a corundum structured crystalline oxide, the crystalline oxide including gallium and/or indium, and the crystalline oxide further including a metal of Group 4 of the periodic table. The crystal is used to make a semiconductor element, and the obtained semiconductor element is used to make a semiconductor device such as a power card. Also, the semiconductor element and the semiconductor device are used to make a semiconductor system.

A method for forming an ohmic contact on a semiconductor component, for example a high-power electrical diode, is provided. An example method includes depositing a first metal layer on a top surface of a semiconductor drift layer having an electrical contact point, the first metal layer highly reflective of a laser light. The method further includes depositing a second metal layer on portions of the first metal layer aligned with the electrical contact point, the second metal layer selected to absorb the laser light. The method further includes exposing the first and the second metal layers to the laser light in a laser annealing process, causing the second metal layer to substantially increase in temperature due to the laser light. The increase in temperature of the second metal layer causing the ohmic contact to form between the electrical contact point and the first metal layer.

A semiconductor device includes a substrate; a channel region disposed in the substrate; and a diffusion region disposed in the substrate on a side of the channel region. The diffusion region comprises a LDD region and a heavily doped region within the LDD region. A gate electrode is disposed over the channel region. The gate electrode partially overlaps with the LDD region. A spacer is disposed on a sidewall of the gate electrode. A gate oxide layer is disposed between the gate electrode and the channel region, between the gate electrode and the LDD region, and between the spacer and the LDD region. A silicide layer is disposed on the heavily doped region and is spaced apart from the edge of the spacer.

A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.