A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern having a first height and the second gate pattern having a second height, an insulating pattern on the substrate covering the first and second gate patterns, the insulating pattern including a trench exposing the substrate between the first and second gate patterns, a spacer contacting at least a portion of a sidewall of the insulating pattern within the trench, the spacer spaced apart from the first and second gate patterns and having a third height larger than the first and second heights, and a contact structure filling the trench.

Field-plate structures are disclosed for electrical field management in semiconductor devices. A field-plate semiconductor device comprises a semiconductor substrate, a first ohmic contact and a second ohmic contact disposed over the semiconductor substrate, one or more coupling capacitors, and one or more capacitively-coupled field plates disposed over the semiconductor substrate between the first ohmic contact and the second ohmic contact. Each of the capacitively-coupled field plates is capacitively coupled to the first ohmic contact through one of the coupling capacitors, the coupling capacitor having a first terminal electrically connected to the first ohmic contact and a second terminal electrically connected to the capacitively-coupled field plate.

A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a gate, a spacer on a sidewall of the gate, a doping region on one side of the gate, an insulating cap layer covering the gate, the spacer and the doping region, and a redistributed contact layer (RCL) on the insulating cap layer. The RCL extends from the active area to the trench isolation region. A contact plug is disposed above the trench isolation region and is electrically connected to the gate or the doping region through the RCL.

An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed.

A method of manufacturing an array substrate is discussed. The method includes forming a gate line on a substrate including a pixel region, forming a gate electrode on the substrate and connected to the gate line, and forming a gate insulating layer on the gate line and the gate electrode. The method further includes forming a data line on the gate insulating layer and crossing the gate line to define the pixel region, forming a source electrode and a drain electrode on the gate insulating layer and corresponding to the gate electrode, the source electrode connected to the data line and the drain electrode spaced apart from the source electrode, and forming an oxide semiconductor layer on top of the source and drain electrodes.

A method of manufacturing a semiconductor device includes forming a first trench in a semiconductor substrate from a first side, forming a semiconductor layer adjoining the semiconductor substrate at the first side, the semiconductor layer capping the first trench at the first side, and forming a contact at a second side of the semiconductor substrate opposite to the first side.

An array substrate for a liquid crystal display device includes a substrate; a semiconductor layer on the substrate; a gate electrode on the semiconductor layer; source and drain electrodes that are on and contact the semiconductor layer; and an oxide layer that corresponds to the semiconductor layer and is on the gate electrode.

A method of manufacturing a silicon carbide semiconductor device is provided. The method suppresses the increase in the number of manufacturing steps and is capable of suppressing the degradation of ohmic characteristics of an alloy layer with respect to a semiconductor substrate. The method includes a step of forming a metal layer made of a first metal on a semiconductor substrate made of silicon carbide; a step of forming a metal nitride film obtained by nitriding a second metal on the metal layer; a step of directing a laser light through the metal nitride film to form a layer of an alloy of silicon carbide in the semiconductor substrate and the first metal in the metal layer; and a step of forming an electrode on the metal nitride film.

In one aspect, methods of silicidation and germanidation are provided. In some embodiments, methods for forming metal silicide can include forming a non-oxide interface, such as germanium or solid antimony, over exposed silicon regions of a substrate. Metal oxide is formed over the interface layer. Annealing and reducing causes metal from the metal oxide to react with the underlying silicon and form metal silicide. Additionally, metal germanide can be formed by reduction of metal oxide over germanium, whether or not any underlying silicon is also silicided. In other embodiments, nickel is deposited directly and an interface layer is not used. In another aspect, methods of depositing nickel thin films by vapor phase deposition processes are provided. In some embodiments, nickel thin films are deposited by ALD.

A semiconductor arrangement is presented. The semiconductor arrangement comprises a semiconductor body, the semiconductor body including a semiconductor drift region, wherein the semiconductor drift region has dopants of a first conductivity type; a first semiconductor sense region and a second semiconductor sense region, wherein each of the first semiconductor sense region and the second semiconductor sense region is electrically connected to the semiconductor drift region and has dopants of a second conductivity type different from said first conductivity type; a first metal contact comprising a first metal material, the first metal contact being in contact with the first semiconductor sense region, wherein a transition between the first metal contact and the first semiconductor sense region forms a first metal-to-semiconductor transition; a second metal contact comprising a second metal material different from said first metal material, the second metal contact being separated from the first metal contact and in contact with the second semiconductor sense region, a transition between the second metal contact and the second semiconductor sense region forming a second metal-to-semiconductor transition different from said first metal-to-semiconductor transition; first electrical transmission means, the first electrical transmission means being arranged and configured for providing a first sense signal derived from an electrical parameter of the first metal contact to a first signal input of a sense signal processing unit; and second electrical transmission means separated from said first electrical transmission means, the second electrical transmission means being arranged and configured for providing a second sense signal derived from an electrical parameter of the second metal contact to a second signal input of said sense signal processing unit.