A semiconductor device comprises a bulk semiconductor substrate that includes a first conductivity type floating buried doped region bounded above by a second conductivity type doped region and bounded below by another second conductivity semiconductor region. Trench isolation regions extend through the second conductivity doped region and the first conductivity floating buried doped region into the semiconductor region. Functional devices are disposed within the second conductivity type doped region. The first conductivity type floating buried doped region is configured as a self-biased region that laterally extends between adjacent trench isolation regions.

A device includes a vertical transistor comprising a first buried layer over a substrate, a first well over the first buried layer, a first gate in a first trench, wherein the first trench is formed partially through the first buried layer, and wherein a dielectric layer and the first gate are in the first trench, a second gate in a second trench, wherein the second trench is formed partially through the first buried layer, and wherein the second trench is of a same depth as the first trench, a first drain/source region and a second drain/source region formed on opposite sides of the first trench and a first lateral transistor comprising a second buried layer formed over the substrate, a second well over the second buried layer and drain/source regions over the second well.

A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in which a structure is manufactured which operates as a Silicon Controlled Rectifier which is coupled between an I/O pad and a reference voltage or ground voltage. The semiconductor device also comprises a pnp transistor which is coupled parallel to the Silicon Controlled Rectifier. The base of the transistor is coupled to the gate of the Silicon Controlled Rectifier. In an optional embodiment, the base and gate are also coupled to the I/O pad.

An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a first shallow trench isolation (STI) around the fin-shaped structure; dividing the fin-shaped structure into a first portion and a second portion; and forming a second STI between the first portion and the second portion.

A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.

A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.

A semiconductor device and a method of forming the same, the semiconductor device includes fin shaped structures and a recessed insulating layer. The fin shaped structures are disposed on a substrate. The recessed insulating layer covers a bottom portion of each of the fin shaped structures to expose a top portion of each of the fin shaped structures. The recessed insulating layer has a curve surface and a wicking structure is defined between a peak and a bottom of the curve surface. The wicking structure is disposed between the fin shaped structures and has a height being about 1/12 to 1/10 of a height of the top portion of the fin shaped structures.