Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes an isolation structure formed over a semiconductor substrate. A first fin structure and a second fin structure extend from the semiconductor substrate and protrude above the isolation structure. A first gate structure is formed across the first fin structure and a second gate structure is formed across the second fin structure. A gate isolation structure is formed between the first fin structure and the second fin structure and separates the first gate structure from the second gate structure. The gate isolation structure includes a bowl-shaped insulating layer that has a first convex sidewall surface adjacent to the first gate structure and a second convex sidewall surface adjacent to the second gate structure.

A method includes providing a substrate, an isolation structure, and a fin extending from the substrate and through the isolation structure. The fin includes a stack of layers having first and second layers that are alternately stacked and have first and second semiconductor materials respectively. A topmost layer of the stack is one of the second layers. The structure further has a sacrificial gate stack engaging a channel region of the fin. The method further includes forming gate spacers and forming sidewall spacers on sidewalls of the fin in a source/drain region of the fin, wherein the sidewall spacers extend above a bottom surface of a topmost one of the first layers. The method further includes etching the fin in the source/drain region, resulting in a source/drain trench; partially recessing the second layers exposed in the source/drain trench, resulting in gaps; and forming dielectric inner spacers inside the gaps.

Disclosed are devices that include a direct N/P local interconnect with minimal recess on shallow trench isolation (STI) oxide. This reduces undesirable coupling capacitance with active gate, which in turn improves AC performance of the device. Pull or even partial replacement of STI oxide with low-k dielectric can further reduce coupling capacitance.

A method includes: forming a first channel structure through a first gate structure; forming a first source/drain structure coupled to the first channel structure at a first surface of the first gate structure; before the first source/drain structure is formed, forming a first isolation layer at a second surface of the first gate structure to isolate the first channel structure; and after the first source/drain structure is formed, forming a first insulation structure at a position of the first isolation layer. The first surface and the second surface are opposite to each other, and a size of the first insulation structure is equal to or larger than a size of the first source/drain structure.

A semiconductor device includes a sensing element including a sensing electrode and a filter covering the sensing electrode. The filter includes a first work function layer and a second work function layer. The first work function layer is over the sensing electrode. The second work function layer is over the first work function layer. A work function value of the second work function layer is greater than a work function value of the first work function layer, and an atomic percentage of metal in the second work function layer is greater than an atomic percentage of metal in the first work function layer.

A semiconductor device includes a substrate having a fin element extending therefrom. In some embodiments, a gate structure is formed over the fin element, where the gate structure includes a dielectric layer on the fin element, a metal capping layer disposed over the dielectric layer, and a metal electrode formed over the metal capping layer. In some cases, first sidewall spacers are formed on opposing sidewalls of the metal capping layer and the metal electrode. In various embodiments, the dielectric layer extends laterally underneath the first sidewall spacers to form a dielectric footing region.

A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.

An integrated circuit includes a first chip bonded to a second chip. The first chip includes gate all around transistors on a substrate. The first chip includes backside conductive vias extending through the substrate to the gate all around transistors. The second chip includes electronic circuitry electrically connected to the transistors by the backside conductive vias.

A microelectronic structure includes a first row of stack nano devices that includes a plurality of a first stacked nano FET devices and a second row of stack nano devices that includes a plurality of a second stacked nano FET devices. Each of the plurality of first nano stacked FET devices and each of the plurality of second stacked FET devices includes an upper stack transistor and a lower stack transistor. A gate cut located between the first row of stacked nano devices and the second row stacked nano devices. An interconnect located within gate cut. The interconnect is connected to a source/drain of one of the lower stacked transistors and the interconnect includes a non-uniform backside surface.

A disclosed structure includes a semiconductor fin on a substrate and an isolation region on the substrate laterally surrounding a lower portion of the fin. A fin-type field effect transistor (FINFET) includes an upper portion of the fin and an isolation structure, and a gate structure are on the isolation region and positioned laterally adjacent to the upper portion of the fin. The gate structure also extends over the top of the fin and abuts the isolation structure. The FINFET also includes an independently biasable supplementary gate structure integrated into the isolation structure. Specifically, an opening extends into the isolation structure adjacent to, but separated from, the fin. The supplementary gate structure includes a conductor layer within the opening and that portion of the isolation structure between the conductor layer and the semiconductor fin. Also disclosed are associated methods.