This invention discloses a semiconductor power device formed in a semiconductor substrate includes rows of multiple horizontal columns of thin layers of alternate conductivity types in a drift region of the semiconductor substrate where each of the thin layers having a thickness to enable a punch through the thin layers when the semiconductor power device is turned on. In a specific embodiment the thickness of the thin layers satisfying charge balance equation q*N.sub.D*W.sub.N=q*N.sub.A*W.sub.P and a punch through condition of W.sub.P<2*W.sub.D*[N.sub.D/(N.sub.A+N.sub.D)] where N.sub.D and W.sub.N represent the doping concentration and the thickness of the N type layers 160, while N.sub.A and W.sub.P represent the doping concentration and thickness of the P type layers; W.sub.D represents the depletion width; and q represents an electron charge, which cancel out. This device allows for a near ideal rectangular electric field profile at breakdown voltage with sawtooth like ridges.

A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

A semiconductor device includes a plurality of epitaxial layers stacked over a supportive substrate, a first buried impurity region formed to share the supportive substrate with a lowermost epitaxial layer among the multiple epitaxial layers, one or more second buried impurity regions formed to be coupled with the first buried impurity region and share an N.sup.th epitaxial layer and an (N+1).sup.th epitaxial layer among the multiple epitaxial layers, where N is a natural number, a body region formed in an uppermost epitaxial layer among the multiple epitaxial layers and a deep well formed in the uppermost epitaxial layer to surround the body region and to be coupled with the second buried impurity regions that share the uppermost epitaxial layer.

Various embodiments of the present disclosure are directed towards an integrated chip including an isolation structure extending into a front-side surface of a substrate. The isolation structure laterally encloses a first device region of the substrate. The isolation structure comprises a pair of isolation edges elongated in a first direction and at least partially defining the first device region. A pair of source/drain regions is disposed within the first device region and laterally spaced from one another in the first direction. A first gate electrode structure is disposed in the first device region between the pair of source/drain regions. The first gate electrode structure comprises a first pair of opposing sidewalls elongated in the first direction. The opposing sidewalls are laterally offset from a corresponding isolation edge in the pair of isolation edges by a non-zero distance in a direction towards a center of the first gate electrode structure.

The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a semiconductor substrate and a drain region disposed within the semiconductor substrate and separated from the source region. A gate electrode is disposed within the semiconductor substrate between the source region and the drain region. The gate electrode includes a base region and a plurality of gate extensions. The plurality of gate extensions are laterally between the base region and the drain region. An inter-level dielectric structure is disposed on an upper surface of the semiconductor substrate and surrounds one or more interconnects. The base region and the plurality of gate extensions are below the upper surface of the semiconductor substrate.

A high-voltage transistor structure is provided that includes a self-aligned isolation feature between the gate and drain. Normally, the isolation feature is not self-aligned. The self-aligned isolation process can be integrated into standard CMOS process technology. In one example embodiment, the drain of the transistor structure is positioned one pitch away from the active gate, with an intervening dummy gate structure formed between the drain and active gate structure. The dummy gate structure is sacrificial in nature and can be utilized to create a self-aligned isolation recess, wherein the gate spacer effectively provides a template for etching the isolation recess. This self-aligned isolation forming process eliminates a number of the variation and dimensional constraints attendant non-aligned isolation forming techniques, which in turn allows for smaller footprint and tighter alignment so as to reduce device variation. The structure and forming techniques are compatible with both planar and non-planar transistor architectures.

A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

A high-voltage transistor structure is provided that includes a self-aligned isolation feature between the gate and drain. Normally, the isolation feature is not self-aligned. The self-aligned isolation process can be integrated into standard CMOS process technology. In one example embodiment, the drain of the transistor structure is positioned one pitch away from the active gate, with an intervening dummy gate structure formed between the drain and active gate structure. The dummy gate structure is sacrificial in nature and can be utilized to create a self-aligned isolation recess, wherein the gate spacer effectively provides a template for etching the isolation recess. This self-aligned isolation forming process eliminates a number of the variation and dimensional constraints attendant non-aligned isolation forming techniques, which in turn allows for smaller footprint and tighter alignment so as to reduce device variation. The structure and forming techniques are compatible with both planar and non-planar transistor architectures.

MOSFET-based IC architectures that mitigate or eliminate the relatively high resistance of extended drift regions in EDMOS and LDMOS devices, resulting in MOSFETs that are reliable, capable of handling relatively high drain voltages, and provide high currents at relatively low drain voltages. Embodiments encompass EDMOS or LDMOS devices that include a secondary transistor comprising a differently-doped well located adjacent at least one drift region and between the drain and the body of the device, with a variably-biased secondary gate structure aligned over the differently doped well. Biasing the secondary gate structure to an OFF state causes the differently-doped well to exhibit high resistance, resulting in a high breakdown voltage for the device. Biasing the secondary gate structure to an ON state causes the differently-doped well to exhibit low resistance, resulting in a reduced drain resistance path that improves the linearity and the error-vector magnitude characteristics of the device.

A method of fabricating a semiconductor device includes creating a device model of a drain extended transistor with a biased field plate, simulating performance of the drain extended transistor using the device model, adjusting the device model based on the simulation to create an adjusted device model to improve a figure of merit, and creating a circuit model of the drain extended transistor based on the adjusted device model. A semiconductor device includes a drain extended transistor having a field relief dielectric layer over a drain drift region, and a biased field plate over the field relief dielectric layer where a position and bias voltage of the field plate are determined by adjusting a device model of the drain extended transistor based on simulated performance of the drain extended transistor using the device model.