A semiconductor device includes a plurality of gate electrodes, and a plurality of stripe contacts, each formed alternately with each of the gate electrodes along a length direction of the gate electrodes. A conductive transistor with a reference potential applied to one of the stripe contacts forming one of a source and a drain is formed. One of the gate electrodes adjacent to one of the stripe contacts forming the other of the source and the drain is used as a first dummy gate electrode. The semiconductor device further includes a metal extending over the first dummy gate electrode to electrically connect together the stripe contacts formed on opposing sides of the first dummy gate electrode, and a pad connected to one of the stripe contacts formed on opposing sides of the first dummy gate electrode, which is provided across the first dummy gate electrode from the conductive transistor.

An electrostatic discharge protection device and a method of making the same. The device includes a device area located on a semiconductor substrate. The device also includes an array of coextensive, laterally spaced fingers located within the device area. Each finger includes an elongate source and an elongate drain separated by an elongate gate. The fingers are electrically connected in parallel for conducting an electrostatic discharge current during an electrostatic discharge event. The device further includes a plurality of body contact regions. A layout of the body contact regions is graded such that a greater number of the body contact regions, larger body contact regions, or both are located towards a periphery of the device area than towards a central part of the device area. The layout of the body contact regions may encourage triggering of the electrostatic discharge protection device within the central part of the device area.

A protection circuit includes a control circuit that controls current between a first wiring and a second wiring and an application circuit that applies a voltage to the control circuit. The control circuit includes a first thin film transistor that controls the current. The application circuit includes second and third thin film transistors that are connected in series. Each of the second and third thin film transistors includes first and second gates. The first gate of the second thin film transistor is connected to the first wiring. The first gate of the third thin film transistor is connected to a connection point between the second and third thin film transistors. The second gates of the second thin film transistor and the third thin film transistor are connected to the second wiring. The application circuit applies a voltage of the connection point to a gate of the first thin film transistor.

An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.

A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source.

A display device includes a first interconnection line, a first data driver, a second interconnection line, an electrostatic discharge (ESD) circuit, and a display panel. The first connection line transmits a data driving signal. The first data driver includes the first interconnection line and output a data signal based on the data driving signal. The second interconnection line passes through the first data driver and transmits a gate driving signal. The ESD) circuit in the first data driver and discharges static electricity transmitted through the second interconnection line. The first gate driver outputs a gate signal based on the gate driving signal transmitted through the second interconnection line. The display panel receives the data signal and the gate signal.

One or more systems and techniques for limiting a voltage potential between an antenna and a radio-frequency switch circuit are provided. A voltage controller comprises a voltage generator, a voltage detection circuit and a switch cell. The voltage detection circuit is coupled to the voltage generator and to the switch cell, and the switch cell is coupled to a voltage source, and to a node between the radio-frequency switch circuit and the antenna. When the voltage potential exceeds a specified threshold, the voltage generator produces a voltage which the voltage detection circuit measures such that the voltage detection circuit activates the switch cell, resulting in a short circuit between the radio-frequency switch circuit and the voltage source. This serves to inhibit the voltage potential from exceeding the specified threshold, for example.

An integrated circuit includes a data processing circuit, an electrostatic discharge (ESD) protection circuit which is connected between a voltage rail and a ground rail and protects the data processing circuit from an ESD event on the voltage rail, and a switch circuit for controlling a connection between the voltage rail and the data processing circuit in response to a control signal.

A display device that includes a substrate having a display region and an adjacent peripheral region is provided, including; a plurality of sub-pixels provided within the display region; a plurality of data lines electrically connected to the sub-pixels; and a first electronic circuit group and a second electronic circuit group provided in the peripheral region, connected to the corresponding data lines. The first electronic circuit group includes a plurality of first electronic circuits, and the second electronic circuit group includes a plurality of second electronic circuits. Two adjacent first electronic circuits are arranged with a first interval therebetween, and the first interval has a first width. Two adjacent second electronic circuits are arranged with a second interval therebetween, and the second interval has a second width. The first width and the second width are different.

An array substrate, an electro-static discharge method thereof and a display device are disclosed. The array substrate includes: a plurality of data lines, a plurality of gate lines, a power signal line, a charge release signal line, a plurality of electro-static discharge units and at least one short circuit ring unit. The charge release signal line and the power signal line are disposed in parallel, two electro-static discharge units are disposed between them to form an electro-static discharge circuit, each gate line and/or each data line is connected with the charge release signal line by one electro-static discharge unit; the short circuit ring unit is connected between the charge release signal line and the power signal line.