Provided is a semiconductor integrated circuit device including a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate, the first N-channel type high withstanding-voltage transistor including a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor including a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface being in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors capable of operating at 30 V or higher are integrated on the N-type semiconductor substrate.

In one embodiment, a group III-V transistor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A clamping device is integrated with the group III-V transistor structure and is electrically connected to the first current carrying electrode a third electrode to provide a secondary current path during, for example, an electrical stress event.

A semiconductor device and a method of making are disclosed. The device includes a substrate, a power field effect transistor (FET), and integrated sensors including a current sensor, a high current fault sensor, and a temperature sensor. The structure of the power FET includes a drain contact region of a first conductivity type disposed in the substrate, a drain drift region of the first conductivity type disposed over the drain contact region, doped polysilicon trenches disposed in the drain drift region, a body region of a second conductivity type, opposite from the first conductivity type, disposed between the doped polysilicon trenches, a source region disposed on a lateral side of the doped polysilicon trenches and in contact with the body region, and a source contact trench that makes contact with the source region and with the doped polysilicon trenches.

An integrated circuit with a boot strap clamp protecting an input/output transistor coupled to a bondpad where the boot strap clamp is comprised of a protection resistor coupled between the input/output transistor and the bondpad and a bootstrap clamp transistor coupled between the drain of the input/output transistor and the gate of the input/output transistor. An integrated circuit with a boot strap clamp protecting an input/output transistor coupled to a bondpad where the boot strap clamp is comprised of a protection resistor coupled between the input/output transistor and the bondpad and a bootstrap clamp diode coupled between the drain of the input/output transistor and the gate of the input/output transistor and a biasing resistor coupled between the gate and source of the input/output transistor.

Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.

An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between a first gate device and a second gate device. The integrated circuit device includes at least one dummy gate between the two epitaxially grown active regions and between the first gate device and the second gate device, wherein each active region is substantially uniform in length. The first gate device and the second device are formed over a first well having a first conductivity type and the dummy gate is formed over a second well having a second conductivity type.

The present disclosure provides an array substrate, a method for manufacturing the same and a display device. The array substrate includes a plurality of signal lines and a connection line electrically connected to the plurality of signal lines. During the formation of each insulation layer on the connection line, a via-hole is formed at a position where the connection line is to be interrupted. In addition, the protection layer is provided to cover the portion of the connection line corresponding to the region where the via-hole is located, so as to protect the connection line. Upon the completion of the insulation layers, the connection line may be interrupted through the via-holes, so as to interrupt electrical connection among the signal lines.

Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal.

A semiconductor device has a power switching component configured to control the flow of current through a load path, a current sensing component configured to sense the current flow through the load path, and an electrostatic discharge ESD protection component configured to protect the current sensing component from an electrostatic discharge. The ESD protection component has an ESD transistor. The ESD transistor has a gate that connected to a discharge path so that the presence of a discharge of a first polarity causes the ESD transistor to switch on to form a further path for dissipation of a discharge.

A semiconductor apparatus can block the voltage from the power source when the voltage from the power source reaches an excessive level, without requiring a larger chip size. Provided is a semiconductor apparatus including a power semiconductor element a gate of which is controlled in response to a control signal, an overvoltage detector configured to detect that a voltage at a collector terminal of the power semiconductor element reaches an overvoltage level, and a block unit configured to, in response to the detection of the overvoltage level, control the gate of the power semiconductor element to transition to an off-voltage. The semiconductor apparatus may further include a reset unit configured to, in response to that the control signal is input that turns on the power semiconductor element, output a reset signal for a predetermined period of time.