H10D62/405

THIN FILM TRANSISTOR HAVING SPINEL SINGLE-PHASE CRYSTALLINE IZTO OXIDE SEMICONDUCTOR
20250022963 · 2025-01-16 ·

A thin film transistor is provided. The thin film transistor comprises a gate electrode, an InZnSn oxide (IZTO) channel layer that overlaps the top or bottom of the gate electrode and has a spinel single-phase crystalline, a gate insulating layer disposed between the gate electrode and the IZTO channel layer, and source and drain electrodes respectively connected to both ends of the IZTO channel layer.

Semiconductor device

A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with high reliability is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. The semiconductor layer, the second insulating layer, and the conductive layer are stacked in this order over the first insulating layer. The semiconductor layer contains indium and oxygen and has a composition falling within a range obtained by connecting first coordinates (1:0:0), second coordinates (2:1:0), third coordinates (14:7:1), fourth coordinates (7:2:2), fifth coordinates (14:4:21), sixth coordinates (2:0:3), and the first coordinates in this order with a straight line in a ternary diagram showing atomic ratios of indium to an element M and zinc. In addition, the element M is one or more of gallium, aluminum, yttrium, and tin.

SiC SEMICONDUCTOR DEVICE

An SiC semiconductor device includes an SiC semiconductor layer having a first main surface and a second main surface, a gate electrode embedded in a trench with a gate insulating layer, a source region of a first conductivity type formed in a side of the trench in a surface layer portion of the first main surface, a body region of a second conductivity type formed in a region at the second main surface side with respect to the source region in the surface layer portion of the first main surface, a drift region of the first conductivity type formed in a region at the second main surface side in the SiC semiconductor layer, and a contact region of the second conductivity type having an impurity concentration of not more than 1.010.sup.20 cm.sup.3 and formed in the surface layer portion of the first main surface.

Oxide semiconductor film and semiconductor device

To provide an oxide semiconductor film having stable electric conductivity and a highly reliable semiconductor device having stable electric characteristics by using the oxide semiconductor film. The oxide semiconductor film contains indium (In), gallium (Ga), and zinc (Zn) and includes a c-axis-aligned crystalline region aligned in the direction parallel to a normal vector of a surface where the oxide semiconductor film is formed. Further, the composition of the c-axis-aligned crystalline region is represented by In.sub.1+Ga.sub.1O.sub.3(ZnO).sub.m (0<<1 and m=1 to 3 are satisfied), and the composition of the entire oxide semiconductor film including the c-axis-aligned crystalline region is represented by In.sub.xGa.sub.yO.sub.3(ZnO).sub.m (0<x<2, 0<y<2, and m=1 to 3 are satisfied).

METHOD FOR SYNTHESIZING NOBLE METAL-SEMICONDUCTOR HETEROSTRUCTURES AND PHOTOCATALYTIC SYSTEM FOR SIMULTANEOUSLY PHOTOCATALYTIC CONVERSION OF CARBON DIOXIDE AND MICROPLASTIC INTO CARBON MONOXIDE
20250031423 · 2025-01-23 ·

A method for synthesizing noble metal-semiconductor heterostructures includes the following steps S1 to S6. Step S1: noble metal seeds are formed. Step S2: at least one metal precursors including a first metal and a first solvent are mixed in a first reactor chamber, so as to obtain a first solution comprising a first mixture. Step S3: the first solution is heated with a first heating process, so as to obtain a transparent solution. Step S4: the noble metal seeds, the transparent solution, and a second solvent are mixed, so as to obtain a second solution. Step S5: the second solution is heated with a second heating process to grow a semiconductor structure containing the first metal on the noble metal seeds, thereby forming the noble metal-semiconductor heterostructures therein. Also, a photocatalytic system including the aforesaid noble metal-semiconductor heterostructures is provided.

SUBSTRATE FOR ELECTRONIC DEVICE AND METHOD FOR PRODUCING THE SAME

A substrate for an electronic device, including a nitride semiconductor film formed on a bonded substrate of a silicon single crystal, in which the bonded substrate is a substrate including a first silicon single-crystal substrate having a crystal plane orientation of {111} and a second silicon single-crystal substrate having a crystal plane orientation of {100} being bonded via an oxide film, the first substrate is formed with a notch in <110> direction, the second substrate is formed with a notch in <011> direction or <001> direction, the <110> direction of the first substrate and the <011> direction of the second substrate are bonded in an angular range of 15 to 15, and the nitride semiconductor film is formed on a surface of the first substrate of the bonded substrate.

FinFET device and method of forming same

A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

Method of manufacturing a semiconductor device and a semiconductor device

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers, the second semiconductor layer and an upper portion of the fin structure at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, are etched. A dielectric layer is formed over the etched upper portion of the fin structure. A source/drain epitaxial layer is formed. The source/drain epitaxial layer is connected to ends of the second semiconductor wires, and a bottom of the source/drain epitaxial layer is separated from the fin structure by the dielectric layer.

Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication

A method of forming a semiconductor structure includes forming an opening in a dielectric layer, forming a recess in an exposed part of a substrate, and forming a lattice-mismatched crystalline semiconductor material in the recess and opening.

Stacked planar double-gate lamellar field-effect transistor

A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.