A method of manufacturing a semiconductor device includes forming electrode trenches in a semiconductor substrate between semiconductor mesas that separate the electrode trenches, the semiconductor mesas including portions of a drift layer of a first conductivity type and a body layer of a second, complementary conductivity type between a first surface of the semiconductor substrate and the drift layer, respectively. The method further includes forming isolated source zones of the first conductivity type in the semiconductor mesas, the source zones extending from the first surface into the body layer. The method also includes forming separation structures in the semiconductor mesas between neighboring source zones arranged along an extension direction of the semiconductor mesas, the separation structures forming partial or complete constrictions of the semiconductor mesa, respectively.

A semiconductor device includes trench gate structures in a semiconductor body with hexagonal crystal lattice. A mean surface plane of a first surface is tilted to a <1-100> crystal direction by an off-axis angle, wherein an absolute value of the off-axis angle is in a range from 2 degree to 12 degree. The trench gate structures extend oriented along the <1-100> crystal direction. Portions of the semiconductor body between neighboring trench gate structures form transistor mesas. Sidewalls of the transistor mesas deviate from a normal to the mean surface plane by not more than 5 degree.

A method for manufacturing a semiconductor device includes a step of preparing a SiC substrate, a step of fixing the SiC substrate on an electrostatic chuck and heat-treating the SiC substrate, and a step of performing ion implantation treatment on the SiC substrate fixed on the electrostatic chuck and heat-treated. The step of heat-treating includes an outer circumferential-side chucking step which generates an electrostatic attraction force between an outer circumferential region of the SiC substrate and an outer circumferential portion of the electrostatic chuck, the outer circumferential portion facing the outer circumferential region, and an inner circumferential-side chucking step which is started after the outer circumferential-side chucking step is started, and generates an electrostatic attraction force between an inner circumferential region of the SiC substrate and an inner circumferential portion of the electrostatic chuck, the inner circumferential portion facing the inner circumferential region.

A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

A semiconductor device includes: an SiC substrate having a first surface and a second surface; a first conductivity type SiC layer disposed on the first surface side of the SiC substrate, and including a low level density region having Z.sub.1/2 level density of 110.sup.11 cm.sup.3 or less measured by deep level transient spectroscopy (DLTS); a second conductivity type SiC region disposed on a surface of the SiC layer; a first electrode disposed on the SiC region; and a second electrode disposed on the second surface side of the SiC substrate.

A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0.

A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.