A method includes forming a fin over a substrate, forming an isolation region adjacent the fin, forming a dummy gate structure over the fin, and recessing the fin adjacent the dummy gate structure to form a first recess using a first etching process. The method also includes performing a plasma clean process on the first recess, the plasma clean process including placing the substrate on a holder disposed in a process chamber, heating the holder to a process temperature between 300 C. and 1000 C., introducing hydrogen gas into a plasma generation chamber connected to the process chamber, igniting a plasma within the plasma generation chamber to form hydrogen radicals, and exposing surfaces of the recess to the hydrogen radicals. The method also includes epitaxially growing a source/drain region in the first recess.

The stability of a step of processing a wiring formed using copper, aluminum, gold, silver, molybdenum, or the like is increased. Moreover, the concentration of impurities in a semiconductor film is reduced. Moreover, the electrical characteristics of a semiconductor device are improved. In a transistor including an oxide semiconductor film, an oxide film in contact with the oxide semiconductor film, and a pair of conductive films being in contact with the oxide film and including copper, aluminum, gold, silver, molybdenum, or the like, the oxide film has a plurality of crystal parts and has c-axis alignment in the crystal parts, and the c-axes are aligned in a direction parallel to a normal vector of a top surface of the oxide semiconductor film or the oxide film.

An optoelectronic device as well as its methods of use and manufacture are disclosed. In one embodiment, an optoelectronic device includes first and second semiconducting atomically thin layers with corresponding first and second lattice directions. The first and second semiconducting atomically thin layers are located proximate to each other, and an angular difference between the first lattice direction and the second lattice direction is between about 0.000001 and 0.5, or about 0.000001 and 0.5 deviant from of a Vicnal angle of the first and second semiconducting atomically thin layers. Alternatively, or in addition to the above, the first and second semiconducting atomically thin layers may form a Moir superlattice of exciton funnels with a period between about 50 nm to 3 cm. The optoelectronic device may also include charge carrier conductors in electrical communication with the semiconducting atomically thin layers to either inject or extract charge carriers.

A semiconductor device according to an embodiment includes a first metal layer, a second metal layer, an n-type first SiC region provided between the first metal layer and the second metal layer and having an n-type impurity concentration of 110.sup.18 cm.sup.3 or less, and a conductive layer provided between the first SiC region and the first metal layer and containing titanium (Ti), oxygen (O), and at least one element selected from the group consisting of vanadium (V), niobium (Nb), and tantalum (Ta).

In a method for forming a device, a (110) silicon substrate is etched to form first trenches in the (110) silicon substrate, wherein remaining portions of the (110) silicon substrate between the first trenches form silicon strips. The sidewalls of the silicon strips have (111) surface orientations. The first trenches are filled with a dielectric material to from Shallow Trench Isolation (STI) regions. The silicon strips are removed to form second trenches between the STI regions. An epitaxy is performed to grow semiconductor strips in the second trenches. Top portions of the STI regions are recessed, and the top portions of the semiconductor strips between removed top portions of the STI regions form semiconductor fins.

Some embodiments of the present disclosure relates to a method of forming a semiconductor device having a strained channel and an associated device. In some embodiments, the method includes performing a first etching process by selectively exposing a substrate to a first etchant to produce a recess defined by sidewalls and a bottom surface of the substrate. An implantation process is performed to form an etch stop layer along the bottom surface. A second etching process is performed by exposing the sidewalls and the bottom surface defining the recess to a second etchant to form a source/drain recess. The source/drain recess laterally extends past the etch stop layer in opposing directions. A semiconductor material is formed within the source/drain recess.

GaN based nanowires are used to grow high quality, discreet base elements with c-plane top surface for fabrication of various semiconductor devices, such as diodes and transistors for power electronics.

A metal oxide semiconductor thin film, a thin film transistor (TFT), methods for fabricating the metal oxide semiconductor thin film and the TFT, and a display apparatus are provided. In some embodiments, the metal oxide semiconductor comprises: a first metal element, a second metal element and a third metal element, wherein: the first metal element is at least one of scandium, yttrium, aluminum, indium, and a rare earth element; the second metal element is at least one of calcium, strontium, and barium; and the third metal element is at least one of titanium and tin.

An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm.sup.1 and less than or equal to 0.7 nm.sup.1 in a region where a magnitude of a scattering vector is greater than or equal to 3.3 nm.sup.1 and less than or equal to 4.1 nm.sup.1. The oxide semiconductor film has a second peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.45 nm.sup.1 and less than or equal to 1.4 nm.sup.1 in a region where a magnitude of a scattering vector is greater than or equal to 5.5 nm.sup.1 and less than or equal to 7.1 nm.sup.1.

Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.