A semiconductor structure includes a substrate and a capacitor over the substrate. The capacitor includes a silicide layer over the substrate. The capacitor includes a first dielectric layer over the silicide layer. The capacitor includes a metal gate structure over the first dielectric layer, where a top portion of the metal gate structure is over the substrate and a bottom portion of the metal gate structure extends into the substrate. The capacitor includes a second dielectric layer over the metal gate structure. The capacitor further includes a conductive structure over the second dielectric layer.

This invention relates to a fin field-effect transistor semiconductor structure. The method of forming the semiconductor structure can include patterning a plurality of precursor fins on a semiconductor layer having a layer portion A and a layer portion B. The semiconductor layer can be located on a substrate. The layer portion B can be selectively etched to form B fins and a top half of precursor fins. The layer portion A can be selectively etched to form A fins and the substrate can be etched to form a bottom half of the decoupling fins. The precursor fins can be removed to expose the A fins, the decoupling fins, and the B fins. One of the A fins and the B fins can form n-type fins and the other can form p-type fins.

A method is provided for forming a metal-insulator-metal capacitor in a replacement metal gate module. The method includes providing a gate cap formed on a gate. The method further includes removing a portion of the gate cap and forming a recess in the gate. A remaining portion of the gate forms a first electrode of the capacitor. The method also includes depositing a dielectric on remaining portions of the gate cap and the remaining portion of the gate. The method additionally includes depositing a conductive material on the dielectric. The method further includes removing a portion of the conductive material and portions of the dielectric to expose a remaining portion of the conductive material and a remaining portion of the dielectric. The remaining portion of the conductive material forms a second electrode of the capacitor. The remaining portion of the dielectric forms an insulator of the capacitor.

High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.

Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. The semiconductor structures may be used as capacitors, for example, in memory devices. Various methods may be used to form such semiconductor structures and capacitors including such semiconductor structures. Memory devices including such capacitors are also disclosed.

A capacitor includes a bottom electrode and a top electrode positioned above the bottom electrode. The top electrode and the bottom electrode are conductively coupled to one another. A middle electrode is positioned between the bottom electrode and the top electrode. A lower dielectric layer is positioned between the bottom electrode and the middle electrode. An upper dielectric layer is positioned between the middle electrode and the top electrode. A first contact is conductively coupled to the top electrode. A second contact is conductively coupled to the middle electrode.

An electrical device including a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material. A first region of the substrate structure includes a first type conductivity semiconductor device having a first strain over a first portion of the relaxed region. A second region of the substrate structure includes a second type conductivity semiconductor device having a second strain over a second portion of the relaxed region. A third region of the substrate structure including a trench capacitor extending into relaxed region, wherein a width of the trench capacitor defined by the end to end distance of the node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surface of the substrate structure.

An electrical device including a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material. A first region of the substrate structure includes a first type conductivity semiconductor device having a first strain over a first portion of the relaxed region. A second region of the substrate structure includes a second type conductivity semiconductor device having a second strain over a second portion of the relaxed region. A third region of the substrate structure including a trench capacitor extending into relaxed region, wherein a width of the trench capacitor defined by the end to end distance of the node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surface of the substrate structure.

The present disclosure relates to an integrated chip having an inter-digitated capacitor, and an associated method of formation. In some embodiments, the integrated chip has a plurality of upper electrodes separated from a substrate by a first dielectric layer. A plurality of lower electrodes vertically extend from between the plurality of upper electrodes to locations embedded within the substrate. A charge trapping dielectric layer is arranged between the substrate and the plurality of lower electrodes and between the plurality of upper electrodes and the plurality of lower electrodes. The charge trapping dielectric layer has a plurality of discrete segments respectively lining opposing sidewalls and a lower surface of one of the plurality of lower electrodes.

A metal-insulator-metal capacitor is provided in a replacement metal gate module having a gate cap formed on a gate. The capacitor includes a first electrode formed within a portion of the gate using a metal forming the gate. The first electrode has a horizontal component and a stack rising from at least a portion of the horizontal component. The capacitor further includes an insulator formed within a recess. The recess is formed to have a lower portion and walls rising from edges of the lower portion. The lower portion is formed on a different portion of the horizontal component than the stack. The walls are formed adjacent to a sidewall of the stack and a portion of the gate cap. The capacitor also includes a second electrode formed within the recess and on the insulator.