An apparatus and associated method for an energy-storage device (e.g., a capacitor) having a plurality of electrically conducting electrodes including a first electrode and a second electrode separated by a non-electrically conducting region, and wherein the non-electrically conducting region further includes a non-uniform permittivity (K) value. In some embodiments, the method includes providing a substrate; fabricating a first electrode on the substrate; and fabricating a second electrode such that the second electrode is separated from the first electrode by a non-electrically conducting region, wherein the non-electrically conducting region has a non-uniform permittivity (K) value. The capacitor devices will find benefit for use in electric vehicles, of all kinds, uninterruptible power supplies, wind turbines, mobile phones, and the like requiring wide temperature ranges from several hundreds of degrees C. down to absolute zero, consumer electronics operating in a temperature range of 55 degrees C. to 125 degrees C.

A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material.

The present disclosure relates to an inter-digitated capacitor that can be formed along with split-gate flash memory cells and that provides for a high capacitance per unit area, and a method of formation. In some embodiments, the inter-digitated capacitor has a well region disposed within an upper surface of a semiconductor substrate. A plurality of trenches vertically extend from the upper surface of the semiconductor substrate to positions within the well region. Lower electrodes are arranged within the plurality of trenches. The lower electrodes are separated from the well region by a charge trapping dielectric layer arranged along inner-surfaces of the plurality of trenches. A plurality of upper electrodes are arranged over the semiconductor substrate at locations laterally separated from the lower electrodes by the charge trapping dielectric layer and vertically separated from the well region by a first dielectric layer.

Back end of the line (BEOL) capacitors and methods of manufacture are provided. The method includes forming wiring lines on a substrate, with spacing between adjacent wiring lines. The method further includes forming an air gap within spacing between the adjacent wiring lines by deposition of a capping material. The method further includes opening the air gap between selected adjacent wiring lines. The method further includes depositing conductive material within the opened air gap.

The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.

The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.

The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate having a first surface, a plurality of layers disposed on the first surface of the substrate. The plurality of layers includes a first nitride layer disposed on the first surface of the substrate, a first silicon-containing layer disposed on the first nitride layer, an intermediate nitride layer disposed on the first silicon-containing layer, a second silicon-containing layer disposed on the intermediate nitride layer, and a second nitride layer disposed on the second silicon-containing layer. In addition, the semiconductor structure includes a trench capacitor penetrating the plurality of layers and in contact with the substrate. The trench capacitor has a first portion having a first lateral surface and a second portion having a second lateral surface, and the first lateral surface has a slope different from that of the second lateral surface.

An OTP memory capacitor structure includes a semiconductor substrate, a bottom electrode, a capacitor insulating layer and a metal electrode stack structure. The bottom electrode is provided on the semiconductor substrate. The capacitor insulating layer is provided on the bottom electrode. The metal electrode stack structure includes a metal layer, an insulating sacrificial layer and a capping layer stacked in sequence. The metal layer is provided on the capacitor insulating layer and is used as a top electrode. The insulating sacrificial layer is provided between the metal layer and the capping layer. A manufacturing method of the OTP memory capacitor structure is also provided. By the provision of the insulating sacrificial layer, the bottom electrode formed first can be prevented from being damaged by subsequent etching and other processes, so that the OTP memory capacitor structure has better electrical characteristics.

The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.