A display device including a pixel electrode portion electrically connected to a thin film transistor; a semiconductor light emitting device configured to emit light to form an individual pixel, and including a conductive electrode; a conductive adhesive layer adhered to the semiconductor light emitting device, and configured to electrically connect the pixel electrode portion to the conductive electrode; and a buffer layer including an elastic material to protect the thin film transistor, and disposed between the thin film transistor and the conductive adhesive layer.

A display device includes a display element, a transistor configured to drive the display element, the transistor including a channel region, and a retention capacitor. An oxide semiconductor film is provided in areas across the transistor and the retention capacitor, the oxide semiconductor film including a first region formed in the channel region of the transistor, and a second region having a lower resistance than that of the first region. The second region is formed in the areas of the transistor and retention capacitor other than in the channel region.

The present disclosure provides an array substrate, its driving method and manufacturing method, and a display device. The array substrate includes a transistor layer arranged on a base, and a first transparent conductive layer, a first insulation layer, a second transparent conductive layer, a second insulation layer and a third transparent conductive layer sequentially arranged on the transistor layer. The first transparent conductive layer covers the transistor layer at a display area, the second transparent conductive layer includes a pattern of touch electrodes, and the third transparent conductive layer includes a pattern of pixel electrodes. Within any pixel area of the display area, the pixel electrode is connected to a pixel electrode connection end of the transistor layer through a via-hole in the first insulation layer and the second insulation layer, and the first transparent conductive layer is provided with an opening at a position corresponding to the via-hole.

An array substrate, a display panel, and a fabrication method of the array substrate are provided. The array substrate comprises a first thin film transistor including a metal oxide thin film transistor, and a second thin film transistor including an amorphous silicon thin film transistor. The first thin film transistor and the second thin film transistor are disposed above a substrate. The first thin film transistor is located in a display region of the array substrate, and the second thin film transistor is located in a peripheral circuit region of the array substrate.

A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes: a base substrate; first electrodes formed on the base substrate; a first insulating layer formed on the base substrate provided with the first electrodes; and second electrodes formed on the base substrate provided with the first insulating layer, at least one curved slit being formed in each of the second electrodes.

A method for manufacturing a thin-film transistor includes: forming a first metal layer of a pattern including a gate on a substrate through pattern formation operations; forming a gate insulation layer on the substrate and the first metal layer and forming an oxide semiconductor layer, of which an orthogonal projection is cast on the gate, on the gate insulation layer within a thin-film transistor area and an etch stop layer on the oxide semiconductor layer, in which two etching operations are applied to the patternized oxide semiconductor layer and etch stop layer; forming a patternized second metal layer on the thin-film transistor area and an exposed portion of the gate insulation layer, forming a patternized insulation protection layer on the substrate and the patternized second metal layer, and forming a patternized pixel electrode on the insulation protection layer.

The present disclosure provides a display panel and a method for forming an array substrate of a display panel. The display panel includes an array substrate which includes a display region and a frame region. The frame region includes a wire region in which first signal wires are formed. Each of the first signal wires includes a first conductive layer and a second conductive layer which are stacked with each other and electrically connected. As such, to obtain the same resistance value as that in prior art, the first signal wires in the present disclosure can be formed with a reduced width. Therefore, the wire region of the array substrate can have a smaller size, and thus the whole frame region of the display panel can be smaller.

The present disclosure relates to an array substrate and manufacturing method for the same, and a display device. The array substrate comprises a plurality of pixel regions, a plurality of gate lines, and a plurality of data lines. The gate line and the data line are respectively connected to corresponding pixel regions. The pixel region comprises a common electrode and a pixel electrode arranged correspondingly. The array substrate also comprises a plurality of shield electrodes. The shield electrode is arranged to shield an electric field generated by a current flowing through the corresponding gate line. The shield electrode and the common electrode are arranged on the same layer and are insulated from each other. Since the shield electrode and the common electrode are insulated from each other, a change in the electrical signal in the shield electrode does not affect the common electrode.

Provided is a method for manufacturing an array substrate, in which a planarization layer mask includes a strip pattern that is provided for forming a groove and has two opposite sides along which taper modification patterns are provided so as to reduce taper of a groove formed in a planarization layer, making a slope thereof less steep, thereby preventing shorting of signal lines caused by residues of metal or ITO in a subsequent operation and thus increasing product yield. For the groove associated portion of an array substrate involving an in-cell touch structure, there is no need to change line for the touch sensing lines so as to lower down the difficulty of the operation and increase product yield.

An array substrate is provided. The array substrate includes: a substrate; a LTPS TFT disposed above the substrate; a planarization layer covering the LTPS TFT; a via hole formed in the planarization layer, wherein the via hole reveals a drain electrode of the LTPS TFT; multiple common electrodes and receiving electrodes disposed separately on the planarization layer, wherein the multiple common electrode function as a driving electrode in a touch stage, and the multiple common electrodes which are disposed separately are connected with each other; a passivation layer which covers the multiple common electrodes and the multiple receiving electrodes and the planarization layer; and a pixel electrode disposed on the passivation layer, wherein, the pixel electrode is contacted with the drain electrode through the via hole. A manufacturing method for the array substrate is also provided. The present invention can reduce one manufacturing process and decrease production cost.