A semiconductor device (100) includes a thin film transistor (5) provided on a substrate and including a gate electrode (12), a gate insulating layer (20) in contact with the gate electrode, an oxide semiconductor layer (18) located so as to partially overlap the gate electrode with the gate insulating layer being located between the oxide semiconductor layer and the gate electrode, a source electrode (14), and a drain electrode (16). The oxide semiconductor layer (18) includes a gate facing region (18g) overlapping the gate electrode as seen in a direction of normal to the substrate; and offset regions (18os, 18od) provided adjacent to the gate facing region, the offset regions not overlapping the gate electrode, the source electrode or the drain electrode as seen in the direction of normal to the substrate. The gate facing region has a carrier concentration in the range of 110.sup.17/cm.sup.3 or greater and 110.sup.19/cm.sup.3 or less.

The present invention provides an array substrate and a manufacturing method thereof, a display panel and a display device, belongs to a field of black-matrix-less display technology, and can solve problems that a conductive reflecting structure in a display panel of prior art affects display effect and external visibility. The array substrate of the present invention comprises a conductive reflecting structure and metal particles provided above the conductive reflecting structure.

The embodiments of the present invention provide a substrate and a manufacturing method thereof, as well as a display device. The substrate comprises: a base substrate, a plurality of gate lines arranged in parallel, a first insulating layer that covers the gate lines, a plurality of data lines located on the first insulating layer and perpendicular to the gate lines, a second insulating layer that covers the data lines, and pixel electrodes of sub-pixel areas enclosed by the data lines and the gate lines; polarizing films that cover the pixel electrodes; and first auxiliary gate lines arranged on the second insulating layer and parallel to the gate lines, at least two portions on each of the first auxiliary gate lines being electrically connected with at least two corresponding portions on the gate line through via holes that penetrate the first insulating layer and the second insulating layer, the first auxiliary gate lines and the polarizing films are formed by performing a same patterning process to a same layer of transparent conductive material. The embodiments of the present invention can reduce signal delay in a display device, and can be used for manufacture of a display.

A manufacturing method includes forming a gate member and a common electrode line on a substrate. A gate insulating layer is formed on the gate member and the common electrode line. A semiconductor member and a data member are formed on the gate insulating layer. A first passivation layer is formed on the semiconductor member and the data member. A plurality of color filters is formed on the first passivation layer. A conductor layer and a second passivation layer are formed on the plurality of color filters. A first contact hole exposes a common electrode. A second contact hole exposes the drain electrode. The first and second contact holes are formed by a photolithography process. A pixel electrode connected to the drain electrode is formed through the first contact hole. A connecting member connected to the common electrode line and the common electrode is formed through the second contact hole.

The present invention provides an OLED display substrate and a manufacture method thereof. The OLED display substrate comprises a substrate (10), a TFT (90) located on the substrate (10), a passivation layer (50) located on the TFT (90), a flat layer (60) located on the passivation layer (50), a connecting electrode (80) being located on the flat layer (60) and contacting the TFT (90), an anode (70) being located on the flat layer (60) and covering the connecting electrode (80), an organic emitting layer (71) located on the anode (70) and a cathode (72) located on the organic emitting layer (71); the connecting electrode (80) contacts the TFT (90) via the contact hole (81) penetrating the flat layer (60) and the passivation layer (50); the anode (70) is electrically connected to the TFT (90) via the connecting electrode (80); the short circuit between the cathode and anode of the OLED display substrate can be prevented for avoiding the current concentration and ensuring the normal illumination of the OLED.

A display device and a method for manufacturing the same are provided. The display device includes a first substrate, a second substrate and a light curable sealant. The first substrate has a displaying area and a non-displaying area, in which the displaying area includes a pixel array, and the non-displaying area includes a driving circuit. The driving circuit includes at least a capacitor which is made of transparent conductive material. The second substrate has an opaque area. The light curable sealant is located between the first substrate and the second substrate. When viewing from a normal vector of the first substrate or the second substrate, the light curable sealant, the capacitor and the opaque area are at least partially overlapped with each other.

A semiconductor device with high aperture ratio is provided. The semiconductor device includes a nitride insulating film, a transistor over the nitride insulating film, and a capacitor including a pair of electrodes over the nitride insulating film. An oxide semiconductor layer is used for a channel formation region of the transistor and one of the electrodes of the capacitor. A transparent conductive film is used for the other electrode of the capacitor. One electrode of the capacitor is in contact with the nitride insulating film, and the other electrode of the capacitor is electrically connected to one of a source electrode and a drain electrode of the transistor.

A display panel including: a cathode electrode formed in a cathode region of the display panel, the cathode electrode entirely covering an active region of the display panel a plurality of pixel units in columns and rows in the active region of the display panel; a ring-shaped edge negative voltage line formed in a ring-shaped edge portion of the cathode electrode configured to supply a negative power supply voltage to the cathode electrode; and a plurality of compensation negative voltage lines connected to the ring-shaped edge negative voltage line, the compensation negative voltage lines extending along a column direction of the display panel and arranged along a row direction of the display panel.

A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate electrode, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are provided over the second insulating layer. The first gate electrode has a region overlapping with the semiconductor layer with the first insulating layer provided therebetween. The second gate electrode has a region overlapping with the semiconductor layer with the second insulating layer provided therebetween. A first region is at least part of a region where the second gate electrode overlaps with the semiconductor layer. A second region is at least part of a region where the pixel electrode is provided. The second insulating layer is thinner in the first region than in the second region.

A manufacturing method of an array substrate comprises: forming a source and a drain of a thin film transistor on a base; forming a first insulation layer; forming an active layer of the thin film transistor; forming a second insulation layer; forming a first via hole and a second via hole in the first insulation layer and the second insulation layer above the source and the drain, by etching, and forming a third via hole and a fourth via hole in the second insulation layer above the active layer, by etching; forming a first connection line connecting the source with the active layer through the first via hole and the third via hole, a second connection line connecting the drain with the active layer and the pixel electrode through the second via hole and the fourth via hole and a pixel electrode.