An array substrate comprising an electrical connection block exposed to its surface. By manufacturing a passivation layer via hole in a passivation layer, a drain electrode or a pixel electrode of a thin-film transistor is exposed, so that the electrical connection block fills the passivation layer via hole and is provided in contact with the drain electrode or the pixel electrode. Thereby, when the electrical characteristic value of a TFT is measured, the pixel probe of a measuring apparatus may be electrically connected with the drain electrode or the pixel electrode by directly contacting the electrical connection block, so that the measuring of the electrical characteristics of the TFT may be realized.

This disclosure relates to an array substrate wiring and manufacturing and repairing method thereof. The array substrate wiring comprises a first wiring formed on the substrate for transmitting electric signals; an insulating layer formed on the first wiring; a second wiring formed on the insulating layer, being opposite to the first wiring, the second wiring being in a hanging state and not transmitting electric signals. By means of such a double layer wiring structure, the holes produced in the insulating layer are blocked using the second wiring in the upper layer, such that the outside moisture cannot reach the first wiring via the holes in the insulating layer, thereby protecting the first wiring for transmitting electric signals from corrosion and scratch.

This semiconductor device (100) includes: a thin-film transistor (101); an interlevel insulating layer (14) including a first insulating layer (12); a first transparent conductive layer (15) formed on the interlevel insulating layer and having a first hole (15p); a dielectric layer (17) covering the side surface of the first transparent conductive layer closer to the first hole; and a second transparent conductive layer (19a) overlapping at least partially with the first transparent conductive layer via the dielectric layer, which has a second hole (17p). The first insulating layer has a third hole (12p). The interlevel insulating layer and dielectric layer have a first contact hole (CH1), the sidewall of which includes the side surfaces of the second and third holes (17p, 12p). At least a part of the side surface of the third hole is aligned with that of the second hole. The second transparent conductive layer contacts with the drain electrode in the first contact hole to form a contact portion (105), which at least partially overlaps with a gate line layer when viewed along a normal to a substrate.

It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is provided with a diffraction grating pattern or with an auxiliary pattern formed of a semi-translucent film having a light intensity reducing function to a photolithography step for forming wires in an overlapping portion of wires. And a conductive film to serve as a lower wire of a two-layer structure is formed, and then, a resist pattern is formed so that a first layer of the lower wire and a second layer narrower than the first layer are formed for relieving a steep step.

A preparation method of a conductive via hole structure, a preparation method of an array substrate and a preparation method of a display device, the preparation method of the array substrate includes: forming a first metal layer (01) including the first metal structure (01a), forming a non-metallic film including a first part corresponding to the first metal structure (01a) and an organic insulating film (40) in sequence; patterning the organic insulating film (40) to form a first organic insulating layer via hole (41) corresponding to the first part; then baking to form an organic insulating layer (40); and then, removing the first part of the non-metallic film to form a non-metallic layer and expose the part of the surface (011) of the first metal structure (01a). This method can avoid the metal structure from being seriously oxidized.

The present disclosure provides, for realization of a flexible display apparatus capable of implementing a slim bezel and a method of manufacturing the same, a flexible display apparatus including: a flexible substrate including a first area having a first hole, a second area having a second hole and arranged corresponding to the first area, and a third area between the first area and the second area; a first wiring covering the first hole and arranged in the first area; and a second wiring covering the second hole, arranged in the second area, and electrically connected to the first wiring via the first hole and the second hole.

In accordance with some embodiments of the disclosed subject matter, a TFT, a related TFT array substrate, fabricating methods thereof, a display panel and a display device containing the same are provided. A method for fabricating a TFT is provided, the method comprising: forming an initial conductive layer on a base substrate; performing an oxidization process to partially oxidize the initial conductive layer to form an oxidized insulating sub-layer and a non-oxidized conductive sub-layer; and forming an active layer, a source electrode and a drain electrode over the oxidized insulating sub-layer.

Disclosed is a power storage element including a positive electrode current collector layer and a negative electrode current collector layer which are arranged on the same plane and can be formed through a simple process. The power storage element further includes a positive electrode active material layer on the positive electrode current collector layer; a negative electrode active material layer on the negative electrode current collector layer; and a solid electrolyte layer in contact with at least the positive electrode active material layer and the negative electrode active material layer. The positive electrode active material layer and the negative electrode active material layer are formed by oxidation treatment.

Fabrication methods of a transparent conductive electrode (301) and an array substrate are provided. The fabrication method of the transparent conductive electrode (301) comprises: forming a sacrificial layer pattern (201) on a substrate (10) having a first region (A1) and a second region (A2) adjacent to each other, wherein the sacrificial layer pattern (201) is located in the second region (A2), and has an upper sharp corner profile formed on a side adjacent to the first region (A1); forming a transparent conductive thin-film (30) in the first region (A1) and the second region (A2) of the substrate (10) with the sacrificial layer pattern (201) formed thereon, wherein a thickness ratio of the transparent conductive thin-film (30) to the sacrificial layer pattern (201) is less than or equal to 1:1.5, and the transparent conductive thin-film (30) is disconnected at the upper sharp corner profile of the sacrificial layer pattern (201), such that at least a part of a side surface of the sacrificial layer pattern (201) facing the first region (A1) is exposed; and removing the sacrificial layer pattern (201) so as to reserve the transparent conductive thin-film (30) in the first region as the transparent conductive electrode (301).

The present invention provides a method for producing a fringe field switching (FFS) array substrate, comprising: forming a gate electrode and a common electrode line on the array substrate; forming a gate electrode insulating layer; forming a layer of pixel electrode ITO; forming a semiconductor active layer; forming a source electrode and a drain electrode; forming an insulating protective layer and a via structure; forming a common electrode. The present invention further provides an FFS array substrate and a display apparatus, the display apparatus comprises the FFS array substrate above.