A manufacturing method of an array substrate structure is disclosed, in which after a common electrode is formed, a reduction resistant layer is first formed on the common electrode before deposition of a second insulation layer in order to prevent the film quality of the common electrode from being affected by a reductive atmosphere generated in a process of directly depositing the second insulation layer on the common electrode thereby reducing the influence on the transmittal of the common electrode caused by the deposition of the second insulation layer on the common electrode and providing the common electrode with increased transmittal and enhancing displaying performance.

An array substrate, a display apparatus applying the same and the assembly method thereof are provided, wherein the array substrate includes a substrate having a plurality of pixels, each of the pixels at least includes a thin film transistor (TFT) device, a first electrode, a second electrode separated from the first electrode all of which are disposed on the substrate. at least one of the first electrode and the second electrode is electrically contacted to the TFT device, and either the first electrode or the second electrode has a magnetic force generator used to generate a magnetic force substantially ranging from 10 gauss to 1000 gauss.

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a gate layer on the substrate; forming a first gate dielectric layer on the gate layer; forming a first channel layer on the first region and a second channel layer on the second region; and forming a first source/drain on the first channel layer and a second source/drain on the second channel layer.

An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed.

An array substrate for a liquid crystal display device includes a substrate; a semiconductor layer on the substrate; a gate electrode on the semiconductor layer; source and drain electrodes that are on and contact the semiconductor layer; and an oxide layer that corresponds to the semiconductor layer and is on the gate electrode.

A display apparatus capable of preventing (or protecting from) permeation of moisture. The apparatus includes a substrate comprising a display area and a peripheral area surrounding the display area; a pad unit located on the peripheral area; an organic insulating layer covering the display area and a part of the peripheral area adjacent to the display area; and an inorganic insulating layer that covers at least a first area when the first area is a part between the organic insulating layer and the pad unit.

A display device with a semiconductor layer sequence includes an active region provided for generating radiation and a plurality of pixels. The display device also includes a carrier. The active region is arranged between a first semiconductor layer and a second semiconductor layer. The semiconductor layer sequence includes a recess, which extends from a major face of the semiconductor layer sequence facing the carrier through the active region into the first semiconductor layer and is provided for electrical contacting of the first semiconductor layer. The carrier includes a number of switches, which are each provided for controlling at least one pixel.

Disclosed is a display device that includes an array substrate that includes a display region and a first non-display region, and includes a signal line connected to a pixel in the display region; a first signal transfer line that is at the first non-display region and transfers a test signal, and a second signal transfer line that transfers a test enable signal; a connection pattern connected to the first signal transfer line; a test transistor that is connected between the signal line and the connection pattern, and is connected to the second signal transfer line; and an electrostatic induction element that includes a dummy device in the form of either a dummy pattern and/or a dummy test transistor, the dummy pattern including a dummy connection pattern connected to the first signal transfer line, the dummy test transistor connected to the second signal transfer line.

A display device is described that has reduced resistance in one or more of the gate, common, data electrical lines that control the operation of the pixels of the display device. Reduced resistance is achieved by forming additional metal and/or metal-alloy layers on the gate, common, and/or data lines in such a manner so that the cross-sectional area of those lines is increased. As a consequence, each such line is formed so as to be thicker than could otherwise be achieving without causing defects in the rubbing process of an alignment layer. Additionally, no widening of these lines is needed, thus preserving the aspect ratio of the device. The gate insulating and semiconducting layers that in part make up the thin film transistors that help control the operation of the pixels of the device may also be designed to take into account the increased thickness of the lines.

The transistor includes a gate electrode, a gate insulating film over the gate electrode, an oxide semiconductor film over the gate insulating film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film on the gate electrode side and a second oxide semiconductor film over the first oxide semiconductor film. The first oxide semiconductor film includes a first region in which an atomic proportion of In is larger than that of M (M is Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf). The second oxide semiconductor film includes a second region in which an atomic proportion of In is smaller than that of the first oxide semiconductor film. The second region includes a portion thinner than the first region.