Unfilled gaps are provided as spacers between gate stacks and electrically conductive source/drain contacts to reduce parasitic capacitance in CMOS structures. Sidewall spacers are removed partially or entirely from portions of the gate stacks and replaced by materials such as amorphous semiconductor materials. Source/drain contacts subsequently formed on source/drain regions adjoin the spacer replacement material. Selective removal of the spacer replacement material leaves unfilled gaps between the source/drain contacts and the gate stacks. The unfilled gaps are then sealed by a dielectric layer that leaves the gaps substantially unfilled.

A semiconductor device includes a substrate including a first fin element, a second fin element, and a third fin element. A first source/drain epitaxial feature is disposed over the first and second fin elements. A first portion of the first source/drain epitaxial feature disposed on the first fin element and a second portion of the first source/drain epitaxial feature disposed on the second fin element merge at a merge point. A second source/drain epitaxial feature is disposed over the third fin element. A first sidewall of the second source/drain epitaxial feature interfaces a first third-fin spacer disposed along a first sidewall of the third fin element. A second sidewall of the second source/drain epitaxial feature interfaces a second third-fin spacer disposed along a second sidewall of the third fin element. The merge point has a first height less than a second height of the first third-fin spacer.

Systems, apparatuses, and methods for reducing the area of a semiconductor structure. A spacing violation may be detected for a gap width used to separate first and second regions of a layer of semiconductor material. In response to detecting the violation, the first and second regions are merged into a combined region, and then a cut mask layer is formed above the combined region. Next, an etch process is performed through the cut mask layer to remove an exposed third region within the combined region, wherein the exposed third region is interposed between first and second region portions of the combined region.

Embodiments are directed to a method of forming a semiconductor device and resulting structures having self-aligned spacer protection layers. The method includes forming a first sacrificial gate adjacent to a second sacrificial gate on a substrate. A dielectric layer is formed on the substrate and above top surfaces of the first and second sacrificial gates. A self-aligned protection region is formed to cover a first portion of the dielectric layer and a second uncovered portion of the dielectric layer is removed. The first portion of the dielectric layer defines a spacer after the second portion of the dielectric layer is removed.

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first fin-shaped structure and a second fin-shaped structure on the substrate; forming a first epitaxial layer on the first fin-shaped structure and a second epitaxial layer on the second fin-shaped structure; and forming a cap layer on the first epitaxial layer and the second epitaxial layer. Preferably, a distance between the first epitaxial layer and the second epitaxial layer is between twice the thickness of the cap layer and four times the thickness of the cap layer.

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a fin extending along a first direction over a substrate and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and a first insulating gate sidewall on a first lateral surface of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate structure. A portion of the source/drain region extends under the insulating gate sidewall for a substantially constant distance along the first direction.

In a p-type field effect transistor, a pair of spacers are formed over the top surface of a substrate. A channel recess cavity includes an indentation in the substrate top surface between the pair of spacers. A gate stack has a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity. A source/drain (S/D) recess cavity has a bottom surface and sidewalls below the substrate top surface. The S/D recess cavity has a portion extending below the gate stack. A strained material is filled the S/D recess cavity.

Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

A method includes forming a spacer layer on a top surface and sidewalls of a patterned feature, wherein the patterned feature is overlying a base layer, A protection layer is formed to contact a top surface and a sidewall surface of the spacer layer. The horizontal portions of the protection layer are removed, wherein vertical portions of the protect layer remain after the removal. The spacer layer is etched to remove horizontal portions of the spacer layer, wherein vertical portions of the spacer layer remain to form parts of spacers.

A semiconductor structure is provided, comprising a substrate (130), a support structure (131), a base region (100), a gate stack, a spacer (240), and a source/drain region, wherein the gate stack is located above the base region (100), and the base region (100) is supported above the substrate (130) by the support structure (131), wherein the support structure (131) has a sigma-shaped lateral cross-section; an isolation structure (123) is formed below edges on both sides of the base region (100), wherein a portion of the isolation structure (123) is connected to the substrate (130); a cavity (112) is formed between the isolation structure (123) and the support structure (131); and a source/drain region is formed on both sides of the base region (100) and the isolation structure (123). Accordingly, a method for manufacturing the semiconductor structure is also provided.