Semiconductor devices and methods are disclosed herein. In one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

Provided is a capacitor structure for a three-dimensional AND flash memory device. The capacitor includes a substrate having a capacitor array region and a capacitor staircase region, a circuit under array (CuA) structure disposed on the substrate, a bottom conductive layer disposed on the CuA structure, a stacked structure disposed on the bottom conductive layer, and pillar structures. The stacked structure includes dielectric layers and conductive layers alternately stacked. The conductive layers in the capacitor staircase region are arranged in a staircase form. The pillar structures are arranged in an array in the capacitor array region and penetrate through the stacked structure and the bottom conductive layer. A part of the conductive layers is 10 electrically connected to a first common voltage source, and the rest of the conductive layers and the bottom conductive layer are electrically connected to a second common voltage source.

A memory device includes a substrate, a unit cell selection transistor on the substrate, and a capacitor structure on the unit cell selection transistor, the capacitor structure comprising a common electrode connected to the unit cell selection transistor, a plurality of plate electrodes facing the common electrode, and a capacitor dielectric layer arranged between the common electrode and the plurality of plate electrodes. The common electrode comprises a vertical extension portion in contact with the unit cell selection transistor and extending in a vertical direction, and a plurality of horizontal extension portions extending in a first horizontal direction from a side wall of the vertical extension portion and apart from each other in the vertical direction. Each of the plurality of plate electrodes extends in a second horizontal direction between the plurality of horizontal extension portions, the second horizontal direction being perpendicular to the first horizontal direction.

The present disclosure provides a manufacturing method of a semiconductor structure, and a semiconductor structure. The manufacturing method of a semiconductor structure includes: forming a plurality of cylindrical capacitors in an initial structure; removing part of the initial structure to form trenches, the trenches expose partial sidewalls of the cylindrical capacitors and a substrate of the initial structure; forming a dielectric layer, the dielectric layer at least covers an exposed surface of each of the cylindrical capacitors; forming a first top electrode, the first top electrode covers a surface of the dielectric layer; and forming a second top electrode, the second top electrode covers a surface of the first top electrode. In an axial direction of each of the cylindrical capacitors, the second top electrode formed in each of the trenches has a discontinuous part, and an air gap is formed in the discontinuous part of the second top electrode.

A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

The present disclosure provides a chip part. The chip part includes: a substrate, a first external electrode and a second external electrode, a capacitor portion disposed on a first main surface of the substrate, a lower electrode including a drawer portion drawn out to the first main surface, a capacitive film disposed on the lower electrode, an upper electrode disposed on the capacitive film, a first electrode film electrically connecting the first external electrode to the lower electrode, and a second electrode film electrically connecting the second external electrode to the upper electrode. The drawer portion includes a first portion disposed in a region between the first external electrode and the second external electrode, and the first electrode film includes a first lower contact portion connected to the first portion.

An example semiconductor device includes a capacitor structure on a substrate. The capacitor structure includes a first electrode structure, a second electrode structure, and a capacitor dielectric layer. The first electrode structure includes first horizontal electrode portions apart from each other in a first direction perpendicular to the substrate and a first conductive pillar connected to each of the first horizontal electrode portions and extending in the first direction. The second electrode structure includes a second conductive pillar extending through the first horizontal electrode portions in the first direction and second horizontal electrode portions apart from each other in the first direction on a side wall of the second conductive pillar and alternately arranged with the first horizontal electrode portions. The capacitor dielectric layer is between the side wall of the second conductive pillar and the first horizontal electrode portions.

A method for forming a semiconductor structure is provided. The method includes forming a contact feature over an insulating layer, forming a first passivation layer over the contact feature, and etching the first passivation layer to form a trench exposing the contact feature. The method also includes forming an oxide layer over the contact feature and the first passivation layer and in the trench, forming a first non-conductive structure over the oxide layer, and patterning the first non-conductive structure to form a gap. The method further includes filling a conductive material in the gap to form a first conductive feature. The first non-conductive structure and the first conductive feature form a first bonding structure. The method further includes attaching a carrier substrate to the first bonding structure via a second bonding structure over the carrier substrate.

A semiconductor device includes a bottom electrode structure disposed over a semiconductor substrate. The bottom electrode structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer from bottom to top. The first metal layer, the third metal layer and the fifth metal layer include a first metal material, and the second metal layer and the fourth metal layer include a second metal material different from the first metal material. The semiconductor device also includes a high-k dielectric structure disposed on opposite sidewalls of the bottom electrode structure. The opposite sidewalls of the bottom electrode structure are step-shaped. The semiconductor device further includes a top electrode structure laterally surrounding the bottom electrode structure and separated from the bottom electrode structure by the high-k dielectric structure.

A semiconductor device includes a bottom electrode structure disposed over a semiconductor substrate. The bottom electrode structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer from bottom to top. The first metal layer, the third metal layer and the fifth metal layer include a first metal material, and the second metal layer and the fourth metal layer include a second metal material different from the first metal material. The semiconductor device also includes a high-k dielectric structure disposed on opposite sidewalls of the bottom electrode structure. The opposite sidewalls of the bottom electrode structure are step-shaped. The semiconductor device further includes a top electrode structure laterally surrounding the bottom electrode structure and separated from the bottom electrode structure by the high-k dielectric structure.