A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 510.sup.21 to about 510.sup.22 atoms/cm.sup.2.

A structure includes a substrate and a tunnel field effect transistor (TFET). The TFET includes a source region disposed in the substrate having an overlying source contact, the source region containing first semiconductor material having a first doping type; a drain region disposed in the substrate having an overlying drain contact, the drain region containing second semiconductor material having a second, opposite doping type; and a gate structure that overlies a channel region between the source and the drain. The source region and the drain region are asymmetric with respect to one another such that one contains a larger volume of semiconductor material than the other one. A method is disclosed to fabricate a plurality of the TFETs using a plurality of spaced apart mandrels having spacers. A pair of the mandrels and the associated spacers is processed to form four adjacent TFETs without requiring intervening lithographic processes.

A die stack assembly includes first and second power semiconductor device dice. The first die has a P type peripheral edge separation structure that extends from the top planar semiconductor surface of the first die all the way to the bottom planar semiconductor surface of the die, and that is doped at least in part with aluminum. The backside of the first die is mounted to the backside of the second die. A metal feature that is not covered with passivation, and that can serve as a bonding pad, is disposed on part of the peripheral edge separation structure. A metal member (for example, a bond wire or metal clip) contacts the metal feature such that an electrical connection is established from the metal member, through the metal feature, through the peripheral edge separation structure of the first die, and to an electrode of the second die.

A method for manufacturing a semiconductor substrate may comprise irradiating a surface of a first semiconductor layer and a surface of a second semiconductor layer with one or more types of first impurity in a vacuum. The method may comprise bonding the surface of the first semiconductor layer and the surface of the second semiconductor layer to each other in the vacuum. The method may comprise applying heat treatment to the semiconductor substrate produced in the bonding. The first impurity may be an inert impurity that does not generate carriers in the first and second semiconductor layers. The heat treatment may be applied such that a width of an in-depth concentration profile of the first impurity contained in the first and second semiconductor layers is narrower after execution of the heat treatment than before the execution of the heat treatment.

A method of forming a horizontal nanosheet device or a horizontal nanowire device includes forming a dummy gate and a series of external spacers on a stack including an alternating arrangement of sacrificial layers and channel layers, deep etching portions of the stack between the external spacers to form electrode recesses for a source electrode and a drain electrode, performing an etch-back on portions of the sacrificial layers to form internal spacer recesses above and below each of the channel layers, forming doped internal spacers in the internal spacer recesses, and forming doped extension regions of the source electrode and the drain electrode by outdiffusion of dopants from the doped internal spacers. The method may also include epitaxially regrowing the source electrode and the drain electrode in the electrode recesses.

A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.

A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.

Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

A method provides a substrate having a top surface; forming a first semiconductor layer on the top surface, the first semiconductor layer having a first unit cell geometry; epitaxially depositing a layer of a metal-containing oxide on the first semiconductor layer, the layer of metal-containing oxide having a second unit cell geometry that differs from the first unit cell geometry; ion implanting the first semiconductor layer through the layer of metal-containing oxide; annealing the ion implanted first semiconductor layer; and forming a second semiconductor layer on the layer of metal-containing oxide, the second semiconductor layer having the first unit cell geometry. The layer of metal-containing oxide functions to inhibit propagation of misfit dislocations from the first semiconductor layer into the second semiconductor layer. A structure formed by the method is also disclosed.

A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.