An embodiment semiconductor device includes an n type layer disposed on a first surface of a substrate, the n type layer including beta-gallium oxide (-Ga.sub.2O.sub.3), a p type layer disposed on the n type layer and including nickel oxide represented by a formula M.sub.yNi.sub.1-yO.sub.x, wherein M is a doping element, x is 0.8x1.0, and y is 0y<1, a first electrode disposed on the p type layer, and a second electrode disposed on a second surface of the substrate opposite the first surface.

In a semiconductor device including a transistor, the transistor is provided over a first insulating film, and the transistor includes an oxide semiconductor film over the first insulating film, a gate insulating film over the oxide semiconductor film, a gate electrode over the gate insulating film, a second insulating film over the oxide semiconductor film and the gate electrode, and a source and a drain electrodes electrically connected to the oxide semiconductor film. The first insulating film includes oxygen. The second insulating film includes hydrogen. The oxide semiconductor film includes a first region in contact with the gate insulating film and a second region in contact with the second insulating film. The first insulating film includes a third region overlapping with the first region and a fourth region overlapping with the second region. The impurity element concentration of the fourth region is higher than that of the third region.

A performance of a semiconductor device including an RC-IGBT is improved. An AlNiSi layer (a layer containing aluminum (Al), nickel (Ni), and silicon (Si)) is formed between a back surface of a semiconductor substrate and a back surface electrode. Thus, a favorable ohmic junction can be obtained between the back surface electrode and an N.sup.+-type layer constituting a cathode region in an embedded diode, and a favorable ohmic junction can be obtained between the back surface electrode and a P-type layer constituting a collector region in an IGBT. The AlNiSi layer contains 10 at % or more of each of the aluminum (Al), the nickel (Ni), and the silicon (Si).

A semiconductor device according to the present invention includes a semiconductor substrate, having an emitter layer of a first conductivity type, a collector layer of a second conductivity type and a drift layer of the first conductivity type sandwiched therebetween, the emitter layer disposed at a front surface side of the semiconductor substrate and the collector layer disposed at a rear surface side of the semiconductor substrate, a base layer of the second conductivity type between the drift layer and the emitter layer, a buffer layer of the first conductivity type between the collector layer and the drift layer, the buffer layer having an impurity concentration higher than that of the drift layer, and having an impurity concentration profile with two peaks in regard to a depth direction from the rear surface of the semiconductor substrate, and a defect layer, formed in the drift layer and having an impurity concentration profile with a half-value width of not more than 2 m in regard to the depth direction from the rear surface of the semiconductor substrate.

An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.

A layered semiconductor includes a base layer including a substrate and a buffer layer, and a drift layer which is disposed on the base layer and is made of GaN and whose conductivity type is an n-type. The drift layer has an average n-type impurity concentration of 1.510.sup.16 cm.sup.3 or less in a radial direction of the substrate, and the difference between the maximum n-type impurity concentration and the minimum n-type impurity concentration is 1.510.sup.15 cm.sup.3 or less.

An epitaxial wafer for a heterojunction bipolar transistor and a heterojunction bipolar transistor that is capable of reducing a base resistance and a turn-on voltage as compared to a conventional technique are provided. In an epitaxial wafer for a heterojunction bipolar transistor that includes a collector layer made of GaAs, a base layer (second base layer) formed on the collector layer and made of InGaAs, and an emitter layer formed on the second base layer and made of InGaP, a base layer (first base layer) made of GaAs is interposed between the collector layer and the second base layer.

In a semiconductor device having a silicon carbide device, a technique capable of suppressing variation in a breakdown voltage and achieving reduction in an area of a termination structure is provided. In order to solve the above-described problem, in the present invention, in a semiconductor device having a silicon carbide device, a p-type first region and a p-type second region provided to be closer to an outer peripheral side than the first region are provided in a junction termination portion, a first concentration gradient is provided in the first region, and a second concentration gradient larger than the first concentration gradient is provided in the second region.

A diode includes: a p-type semiconductor substrate; an n-type semiconductor layer; a p-type isolation region formed to surround a predetermined region of the n-type semiconductor layer on the p-type semiconductor substrate; an n-type buried layer formed across the p-type semiconductor layer and the n-type semiconductor layer within the predetermined region; an n-type collector wall formed in the n-type semiconductor layer; a p-type anode region and a plurality of n-type cathode regions formed in a diode formation region; and a p-type guard ring formed to surround the diode formation region in a region between the diode formation region of the surface layer of the n-type semiconductor layer and the p-type isolation region. A transistor for reducing a leakage current is formed by the p-type anode region, the p-type guard ring, and an n-type semiconductor between the p-type anode region and the p-type guard ring.

A JFET has a semiconductor body with a first surface and second surface substantially parallel to the first surface. A source metallization and gate metallization are arranged on the first surface. A drain metallization is arranged on the second surface. In a sectional plane substantially perpendicular to the first surface, the semiconductor body includes: a first semiconductor region in ohmic contact with the source and drain metallizations, at least two second semiconductor regions in ohmic contact with the gate metallization, spaced apart from one another, and forming respective first pn-junctions with the first semiconductor region, and at least one body region forming a second pn-junction with the first semiconductor region. The at least one body region is in ohmic contact with the source metallization. At least a portion of the at least one body region is, in a projection onto the first surface, arranged between the two second semiconductor regions.