A semiconductor device comprises: a semiconductor device active region; an electrode shape controlling layer disposed on the semiconductor device active region, the electrode shape controlling layer containing aluminum, the content of aluminum being changed in a direction from bottom to up from the semiconductor device active region, an electrode region being disposed on the electrode shape controlling layer, a groove extended toward the semiconductor device active region and penetrating through the electrode shape controlling layer longitudinally being disposed in the electrode region, all or part of a side surface of the groove having a shape corresponding to the content of aluminum in the electrode shape controlling layer; and an electrode disposed in the groove in the electrode region entirely or partially, the electrode having a shape matching with the shape of the groove, a bottom portion of the electrode being contacted with the semiconductor device active region.

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region.

One embodiment describes a method of manufacturing a semiconductor device. Here, impurities are implanted into a semiconductor body via a first side of the semiconductor body. Thereafter, a drift zone layer on the first side of the semiconductor body is formed. The following is an ablation of the semiconductor body from a second side of the semiconductor body and up to pn junction defined by impurities.

In an IGBT portion, a first gate electrode is provided in a first trench via a first gate insulating film. A thickness of a first gate insulating film lower portion is thicker than a thickness of a first gate insulating film upper portion, whereby a width of a mesa portion between adjacent first trenches is narrower at a portion of a collector side than at an emitter side. In a diode portion, a second gate electrode is provided inside a second trench via second gate insulating film. A width of the second trench is uniform along a depth direction or narrows from the emitter side toward the collector side. Widths of the second trench are narrower than a sum of a width of the first trench lower portion and the thickness of the first gate insulating film lower portion of both side walls of the first trench lower portion.

Embodiments include methods of forming a semiconductor device having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a source region of the first conductivity type, and the diode circuit is connected between the isolation structure and the source region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).

Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a method for forming a semiconductor device includes forming a first epitaxial layer on sidewalls of trenches and forming second epitaxial layer on the first epitaxial layer where charges in the doped regions along the sidewalls of the first and second trenches achieve charge balance in operation. In another embodiment, the semiconductor device includes a termination structure including an array of termination cells.

Monolithic integration of low-capacitance p-n junctions and low-resistance p-n junctions (when conducting in reverse bias) is provided. Three epitaxial layers are used. The low-capacitance junctions are formed by the top two epitaxial layers. The low-resistance p-n junction is formed in the top epitaxial layer, and two buried structures at interfaces between the three epitaxial layers are used to provide a high doping region that extends from the low-resistance p-n junction to the substrate, thereby providing low resistance to current flow. The epitaxial layers are lightly doped as required by the low-capacitance junction design, so the buried structures are needed for the low-resistance p-n junction. The high doping region is formed by diffusion of dopants from the substrate and from the buried structures during thermal processing.

A semiconductor device for driving a load includes: a protection circuit configured to be connected to the load, the protection circuit including a protection diode, a diode-connected unipolar protection element, and a diode-connected bipolar protection element, all of which are connected in parallel so that when connected to the load, the protection diode, the diode-connected unipolar protection element, and the diode-connected bipolar protection element are connected in parallel to the load; and a switching circuit that is connected in series to the protection circuit and that performs a switching operation so as to drive the load. The protection diode, the diode-connected unipolar protection element, and the diode-connected bipolar protection element are connected in such a polarity that each is reverse-biased when the switching circuit is turned ON, and consume a discharge current resulting from a counter-electromotive force from the load when the switching circuit is turned OFF.

A MOS P-N junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a central conductive layer, a silicon nitride layer, a metal diffusion layer, a channel region, and a metal sputtering layer. For manufacturing the MOS P-N junction diode, a mask layer is formed on a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate, and a polysilicon structure is formed on the gate oxide layer. A guard ring, a central conductive layer and a channel region are formed in the semiconductor substrate. A silicon nitride layer is formed on the central conductive layer. A metal diffusion layer is formed within the guard ring and the central conductive layer. Afterwards, a metal sputtering layer is formed, and the mask layer is partially exposed.

A semiconductor device includes at least one first contact region of a vertical device between a semiconductor substrate and an electrically conductive structure arranged adjacent to the semiconductor substrate, and at least one second contact region of the vertical device between the semiconductor substrate of the semiconductor device and the electrically conductive structure. The at least one first contact region is arranged adjacent to the at least one second contact region. The electrically conductive structure includes a first electrically conductive material in contact with the semiconductor substrate in an area of the at least one first contact region and a second electrically conductive material in contact with the semiconductor substrate in an area of the at least one second contact region, so that a first contact characteristic within the at least one first contact region differs from a second contact characteristic within the at least one second contact region.