A semiconductor device includes an active region formed in an upper layer portion of a semiconductor layer of a first conductivity type, and a plurality of electric field relaxation layers disposed from an edge of the active region toward the outside so as to surround the active region. The plurality of electric field relaxation layers include a plurality of first electric field relaxation layers and a plurality of second electric field relaxation layers alternately disposed adjacent to each other, the first electric field relaxation layer and the second electric field relaxation layer adjacent to each other forming a set. Impurities of a second conductivity type are implanted to the first electric field relaxation layers at a first surface density, widths of which becoming smaller as apart from the active region. Impurities of the second conductivity type are implanted to the second electric field relaxation layers at a second surface density lower than the first surface density, widths of which becoming larger as apart from the active region.

A semiconductor device may include a diode pattern including a first conductive region and a second conductive region having opposite conductivity types to each other on a base insulating layer, an insulating layer covering the diode pattern on the base insulating layer, a wiring portion on the insulating layer; and a through connector extending through the insulating layer at a periphery of the diode pattern to electrically connect the diode pattern and the wiring portion.

A semiconductor device has an active area and a terminal area surrounding the active area and includes a base region, a plurality of annular subregions, an insulating layer provided with a plurality of insulating layer openings, and a first conductive layer. The plurality of annular subregions includes a first annular subregion in contact with the base region. The first annular subregion includes a plurality of annular structures in contact with each other. All the annular structures contact the first conductive layer through the corresponding insulating layer openings. The base region, the annular subregions, and the annular structures have a second conductivity type.

A semiconductor device includes a passive device over vertically stacked epitaxial layers of a first material and a second material, and a field-effect transistor (FET) adjacent to the passive device. A backside of the passive device and a backside of the PET are directly in contact with a backside metal via a bottom interlayer dielectric (BILD).

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate and an epi layer on an upper surface of the substrate. The semiconductor device also includes a P region located within the epi layer, at least one N+ region located within the P region, and at least one insulating layer in contact with the epi layer, the epi layer, the P region, and the at least one N+ region. The semiconductor device further includes an anode on the P region, the N+ region, and the insulating layer.

A semiconductor device is provided. The semiconductor device includes a stacked field effect transistor (FET) formed on a substrate and connected to a backside metal line of a backside power distribution network (BSPDN). The semiconductor device also includes a lateral junction diode co-integrated with the stacked nanosheet FET.

A semiconductor device includes a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an IGBT arranged therein, and a withstand-voltage retention region surrounding the first region and the second regions in plan view are defined. The semiconductor substrate has a first main surface and a second main surface. The semiconductor substrate includes an anode layer having a first conductivity type, which is arranged in the first main surface of the first region, and a diffusion layer having the first conductivity type, which is arranged in the first main surface of the withstand-voltage retention region adjacently to the anode layer. A first trench is arranged in the first main surface on a side of the anode layer with respect to a boundary between the anode layer and the diffusion layer.

In an example, a semiconductor device includes a cathode region having a first conductivity type and a cathode region dopant concentration. A charge storage region overlies the cathode region and has the first conductivity type and a charge storage region dopant concentration less than the cathode region dopant concentration. A buffer region overlies the charge storage region and has the first conductivity type, a buffer region thickness, a buffer region dopant concentration profile, and a buffer region peak dopant concentration. A drift region overlies the buffer region and has the first conductivity type and a drift region dopant concentration. An anode region of a second conductivity type opposite to the first conductivity type is adjacent to the drift region. The buffer region peak dopant concentration is greater than the charge storage region dopant concentration and greater than the drift region dopant concentration. The buffer region peak dopant concentration is spaced apart from the charge storage region and spaced apart from the drift region. Other related examples and methods are disclosed herein.

There is provided a semiconductor device that includes a semiconductor substrate, which has an upper surface and a lower surface, and a drift region of an n-type conductivity provided at a position including the center of the semiconductor substrate in a depth direction connecting the upper surface and the lower surface. Over the entire part of the drift region in the depth direction, a donor concentration of the drift region is higher than a base doping concentration of the semiconductor substrate.

An electron extraction type free-wheeling diode device and a preparation method thereof are provided by the present disclosure, and more than one first structures for increasing the density of electron extraction pathways are provided on a N-type drift region. Each of the first structures includes a lightly doped P-type base region, a heavily doped N-type emitter region located on the lightly doped P-type base region, a P-type trench anode region, and a trench region located on the P-type trench anode region. The barrier height of the punch-through NPN triode can be tuned in a wide range, which has beneficial effects on soft and fast adjustment of the reverse recovery process.