A semiconductor device includes a P-type body region and an N-type drift region disposed in a substrate; a gate electrode, disposed on the P-type body region and the N-type drift region, including a high concentration doping region and a high resistance region, wherein a dopant concentration of the high concentration doping region is higher than a dopant concentration of the high resistance region; a spacer disposed on a side of the gate electrode; a highly doped source region disposed in the P-type body region; and a highly doped drain region disposed in the N-type body region. The high concentration doping region overlaps the P-type body region, and the high resistance region overlaps the N-type drift region.

The application relates to a semiconductor die including a device in an active area of the die. The device includes a field electrode region formed in a field electrode trench extending vertically into a semiconductor body. The field electrode region includes a first and a second field electrode stacked vertically above each other in the field electrode trench. An edge termination structure laterally between the active area and a lateral edge region of the die includes a first and a second shield electrode arranged laterally consecutive between the active area and the lateral edge region to stepwise decrease an electrical potential between the edge region and the active area.

Power semiconductor devices include a semiconductor layer structure comprising an active area with a plurality of unit cell transistors and an inactive gate pad area, a gate resistor layer on an upper side of the semiconductor layer structure, an inner contact that is directly on the upper side of the gate resistor layer, and an outer contact that is directly on the upper side of the gate resistor layer. The outer contact encloses the inner contact within the inactive gate pad area of the semiconductor device.

Proposed are a high voltage semiconductor device and a method of manufacturing the same and, more particularly, a high voltage semiconductor device and a method of manufacturing the same seeking to improve on-resistance (Rsp) characteristics of the device by forming a field plate on a substrate and above a gate region, and prevent deterioration of HE-SOA characteristics by forming a thin film-shaped gate field plate below the gate region to mitigate an electric field concentrated below the field plate and on an edge of the gate region.

A termination structure of a super-junction power device has a novel polysilicon resistive field plate at the top of a termination region between a transition region and an edge of the device. By utilizing the regular distribution of potential in the field plate, an additional electric field is introduced at the top of the termination structure to limit the expansion of a non-depletion region and optimize the distribution of charges. The termination structure includes a first doping type epitaxial layer, a second doping type compensation region, a second doping type body region, a second doping type lateral connection layer, a second doping type body contact region, a first doping type source contact region, a gate oxide layer, a passivation layer, a field oxide layer, a gate electrode, a second doping type edge contact region, a polysilicon resistive field plate, a metal layer and the like.

The disclosure provides a power semiconductor device and manufacturing method thereof. A plurality of second resistive field plate structures extending through an epitaxial layer in a first direction into a substrate are arranged in a termination region of the epitaxial layer and the plurality of second resistive field plate structures are arranged radially in a first plane. A plurality of tightly coupled second resistive field plates extending from a side close to a cell region to a side far away from the cell region form a more uniform three-dimensional electric field distribution diverging around the cell region, which optimizes a guiding and binding effect on a charge in a space depletion region of the cell region and improves a withstand voltage performance of the whole power semiconductor device.

Various embodiments of the present disclosure are directed towards a semiconductor device comprising a plurality of quasi field plates (QFPs) for enhanced wafer uniformity and performance. A channel layer and a barrier layer are stacked on a substrate, and the channel layer accommodates a two-dimensional carrier gas (2DCG). A source electrode, a drain electrode, and a gate electrode overlie the channel and barrier layers, and the gate electrode is between the source and drain electrodes in a first direction. The plurality of QFPs are between the gate electrode and the drain electrode. Further, the plurality of QFPs are capacitively or directly electrically coupled to the drain electrode, and are spaced from each other laterally in a line in a second direction transverse to the first direction.

The MOS device with resistive field plate for realizing conductance modulation field effect in the present invention is based on the existing trench gate MOS device, and a semi-insulating resistive field plate electrically connected to the trench gate structure and the drain structure is added in the drift region, where the trench gate structure can control the on-off of the MOS channel, and the semi-insulating resistive field plate can adjust the doping concentration of the drift region to modulate the conductance of the on-state drift region and the distribution of off-state high-voltage blocking electric field, thus a lower on-resistance can be obtained. In addition, the modern 2.5-dimensional processing technology based on deep trench etching is adopted in the present invention, which is conducive to the miniaturization design and high density design of the structure and is more suitable for the More than Moore (beyond Moore) development of modern integrated semiconductor devices.

We herein describe a power semiconductor device having a semiconductor substrate including an active region and an edge termination region surrounding the active region, an edge termination structure located in the edge termination region of the semiconductor substrate, and a plurality of oxide segments located over the upper surface of the edge termination region of the semiconductor substrate, where the plurality of oxide segments are laterally spaced from each other. The power semiconductor device also includes a charge dissipation layer located over the upper surface of the edge termination region of the semiconductor substrate and the plurality of oxide segments, such that the charge dissipation layer is in contact with the upper surface of the semiconductor substrate only at a plurality of interface regions, where the interface regions comprise regions of the semiconductor substrate located laterally between adjacent oxide segments.

A semiconductor device of embodiments includes: a semiconductor layer having a first face and a second face and including a first trench provided on a first face side; a first field plate electrode provided in the first trench; a gate electrode provided in a gate trench; a first electrode provided on the first face side of the semiconductor layer and electrically connected to the first field plate electrode; a second electrode provided on the second face side of the semiconductor layer; and a connection portion provided between the first electrode and the first field plate electrode, electrically connected to the first electrode and the first field plate electrode, and having an electrical resistance higher than an electrical resistance of the first field plate electrode.