A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.

Integrated circuit structures including a pillar resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor over the substrate. Following embodiments herein, a small resistor footprint may be achieved by orienting the resistive length orthogonally to the substrate surface. In embodiments, the vertical resistor pillar is disposed over a first end of a conductive trace, a first resistor contact is further disposed on the pillar, and a second resistor contact is disposed over a second end of a conductive trace to render the resistor footprint substantially independent of the resistance value. Formation of a resistor pillar may be integrated with a replacement gate transistor process by concurrently forming the resistor pillar and sacrificial gate out of a same material, such as polysilicon. Pillar resistor contacts may also be concurrently formed with one or more transistor contacts.

A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.

A method includes forming an insulating carrier substrate, forming a shallow trench isolation region within the insulating carrier substrate, and forming a plurality of gate recesses on the shallow trench isolation region. The plurality of gate recesses is formed by forming a plurality of dummy gates on the shallow trench isolation region and etching the plurality of dummy gates. The method further includes depositing a metal resistor layer within the plurality of gate recesses.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

A semiconductor device including a carrier having two main surfaces situated opposite one another, a circuit, having at least one resistance element, in and/or on the carrier, wherein the at least one resistance element has a longitudinal axis extending vertically between the main surfaces of the carrier, and a current limiting circuit configured to limit a current flowing through the resistance element to a value at which it is ensured that an electrical resistance of the resistance element remains substantially unchanged.

A thin-film resistor and a method for fabricating a thin-film resistor are provided. The thin-film resistor comprises a first terminal, a second terminal, and a resistor body providing a resistive current path between the first terminal and the second terminal, and the method comprises depositing a first layer of conductive material onto at least one of the supporting structure and the resistor body, applying a first lithographic mask to the first layer, and etching the first layer to form the first terminal; and depositing a second layer of conductive material onto at least one of the supporting structure and the resistor body, applying a second lithographic mask to the second layer, and etching the second layer to form the second terminal, wherein the first lithographic mask is different to the second lithographic mask, and a lateral separation of the first terminal and the second terminal is less than an in-plane minimum feature size of the first and second lithographic masks

Semiconductor structures having low resistance via contacts and methods of fabricating the same are provided. An example semiconductor structure includes a substrate, a dielectric layer disposed over the substrate, a resistor disposed in the dielectric layer, and a resistor via contact disposed in the dielectric layer the resistor. The resistor via contact further includes a first layer disposed on and in contact with the resistor, a second layer disposed on the first layer, and a third layer disposed on the second layer. The first layer has a first thickness and includes a first material having a first resistivity, the second layer has a second thickness and includes a second material, and the third layer has a third thickness and includes a third material having a second resistivity. The first thickness is more than the third thickness, and the first resistivity is less than the second resistivity.

Disclosed is a fan-out package in which two or more dies are integrated in a fan-out packaging process, wherein the fan-out package includes a bridge structure including a bridge substrate formed on one side of the fan-out package, a redistribution layer formed on the bridge substrate, the redistribution layer including at least one trace, the redistribution layer being configured to electrically connect the dies to each other, and a passive element formed in the redistribution layer by patterning. The routing density of the trace is relieved, and electrical performance is improved by the provision of the passive element.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.