A solid-state imaging device includes, in a semiconductor substrate, a pixel portion provided with a photoelectric conversion portion, which photoelectrically converts incident light to obtain an electric signal and a peripheral circuit portion disposed on the periphery of the pixel portion, wherein a gate insulating film of aMOS transistor in the peripheral circuit portion is composed of a silicon oxynitride film, a gate insulating film of aMOS transistor in the pixel portion is composed of a silicon oxynitride film, and an oxide film is disposed just above the photoelectric conversion portion in the pixel portion.

Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an interior of the first insulative structure, and a ferroelectric structure lines an interior of the first conductive structure. A second conductive structure is within a lower region of the ferroelectric structure, and the second conductive structure has an uppermost surface beneath an uppermost surface of the first conductive structure. A second insulative structure is over the second conductive structure and within the ferroelectric structure. A pair of source/drain regions are adjacent an upper region of the first insulative structure and are on opposing sides of the first insulative structure from one another.

An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.

The present inventive concept relates to a thin film manufacturing method and a thin film. The thin film manufacturing method comprises: an adsorption step of adsorbing a high-k material on a substrate by spraying a source gas consisting of a high-k material; a deposition step of depositing a thin film consisting of the high-k material on the substrate by spraying a reaction gas that reacts with the source gas; and a crystallization step of crystallizing the high-k material using plasma.

A semiconductor device according to one or more embodiments is disclosed that may include a p-type first semiconductor region, an n-type second semiconductor region formed on a surface of the first semiconductor region, an n-type third semiconductor region formed by separating from the second semiconductor region, an n-type fourth semiconductor region having a higher impurity concentration than the second semiconductor region, an insulating film arranged on the semiconductor substrate, a gate electrode arranged via the insulating film between the second semiconductor region and the third semiconductor region, a first main electrode electrically connected to the second semiconductor region, a second main electrode electrically connected to the fourth semiconductor region, a p-type fifth semiconductor region on the third semiconductor region, which has a higher impurity concentration than that of the first semiconductor region, and an auxiliary electrode connected to the fifth semiconductor region.

A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions.

A process for depositing titanium aluminum or tantalum aluminum thin films comprising nitrogen on a substrate in a reaction space can include at least one deposition cycle. The deposition cycle can include alternately and sequentially contacting the substrate with a vapor phase Ti or Ta precursor and a vapor phase Al precursor. At least one of the vapor phase Ti or Ta precursor and the vapor phase Al precursor may contact the substrate in the presence of a vapor phase nitrogen precursor.

A metal gate stack on a substrate comprises: an interfacial layer on the substrate; a high- metal oxide layer on the interfacial layer, the high- metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region comprising niobium (Nb); a high- metal oxide capping layer on the high- metal oxide layer; a positive metal-oxide-semiconductor (PMOS) work function material above the high- metal oxide capping layer; and a gate electrode above the PMOS work function material. The dipole region is formed by driving Nb species of a Nb-based film into the high- metal oxide layer to form a dipole region.