The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a III-nitride layer, a gate, a connection structure, and a gate bus. The gate is disposed over the III-nitride layer. The connection structure is disposed over the gate. The gate bus extends substantially in parallel to the gate and disposed over the connection structure from a top view perspective. The gate bus is electrically connected to the gate through the connection structure.

The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor and methods of manufacture. The structure includes: a gate structure; a first field plate on a first side of the gate structure; and a second field plate on a second side of the gate structure, independent from the first field plate.

A nitride semiconductor device including a substrate, a channel layer, a carbon-poor barrier layer having a recess, a carbon-rich barrier layer disposed over the recess and the carbon-poor barrier layer, and a gate electrode above the recess, wherein the carbon-poor and carbon-rich barrier layers have bandgaps larger than that of the channel layer, the upper surface of the carbon-rich barrier layer includes a first main surface including a source electrode and a drain electrode, and a bottom surface of a depression disposed along the recess, and side surfaces of the depression connecting the first main surface to the bottom surface of the depression, and among edges of the depression of the carbon-rich barrier layer which are boundaries between the first main surface and the side surfaces of the depression, the edge of the depression of the carbon-rich barrier layer closest to the drain electrode is covered with the gate electrode.

A field effect transistor comprising a buffer and channel layer formed successively on a substrate. A source electrode, drain electrode, and gate are all formed in electrical contact with the channel layer, with the gate between the source and drain electrodes. A spacer layer is formed on at least a portion of a surface of the channel layer between the gate and drain electrode and a field plate is formed on the spacer layer isolated from the gate and channel layer. The spacer layer is electrically connected by at least one conductive path to the source electrode, wherein the field plate reduces the peak operating electric field in the device.

In an embodiment, a semiconductor device includes a Group III-nitride-based High Electron Mobility Transistor (HEMT) configured as a bidirectional switch. The Group III nitride-based HEMT includes a first input/output electrode, a second input/output electrode, a gate structure arranged between the first input/output electrode and the second input/output electrode, and a field plate structure.

Field-plate structures are disclosed for electrical field management in semiconductor devices. A field-plate semiconductor device comprises a semiconductor substrate, a first ohmic contact and a second ohmic contact disposed over the semiconductor substrate, one or more coupling capacitors, and one or more capacitively-coupled field plates disposed over the semiconductor substrate between the first ohmic contact and the second ohmic contact. Each of the capacitively-coupled field plates is capacitively coupled to the first ohmic contact through one of the coupling capacitors, the coupling capacitor having a first terminal electrically connected to the first ohmic contact and a second terminal electrically connected to the capacitively-coupled field plate.

A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervenes therebetween.

There are disclosed herein various implementations of a III-Nitride bidirectional device. Such a bidirectional device includes a substrate, a back channel layer situated over the substrate, and a device channel layer and a device barrier layer situated over the back channel layer. The device channel layer and the device barrier layer are configured to produce a device two-dimensional electron gas (2DEG). In addition, the III-Nitride bidirectional device includes first and second gates formed on respective first and second depletion segments situated over the device barrier layer. The III-Nitride bidirectional device also includes a back barrier situated between the back channel layer and the device channel layer. A polarization of the back channel layer of the III-Nitride bidirectional device is substantially equal to a polarization of the device channel layer.

Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least two gaps of the plurality of gaps. The plurality of tines have proximal ends connected to the main body of the gate, middle portions projecting through the plurality of gaps, and distal ends separated from the first piezoelectric layer by at least the second piezoelectric layer. The dielectric layer exerts stress, creating a piezoelectric charge in the first piezoelectric layer, changing the threshold voltage of the transistor.

A nitride semiconductor device includes a substrate; a nitride semiconductor multilayer structure which is formed on the substrate, includes a first nitride semiconductor layer and a second nitride semiconductor layer having a different composition from that of the first nitride semiconductor layer, and generates two dimensional electron gas on a hetero interface between the first nitride semiconductor layer and the second nitride semiconductor layer; and an insulating film which covers at least a portion of a surface of the nitride semiconductor multilayer structure, has a concentration of SiH bonds equal to or less than 6.010.sup.21 cm.sup.3, and is formed of silicon nitride.