A semiconductor device 1 has an electrode structure that includes source electrodes 3, a gate electrode 4, and drain electrodes 5 disposed on a semiconductor laminated structure 2 and extending in parallel to each other and in a predetermined first direction and a wiring structure that includes source wirings 9, drain wirings 10, and gate wirings 11 disposed on the electrode structure and extending in parallel to each other and in a second direction orthogonal to the first direction. The source wirings 9, the drain wirings 10, and the gate wirings 11 are electrically connected to the source electrodes 3, the drain electrodes 5, and the gate electrode 4, respectively. The semiconductor device 1 includes a conductive film 8 disposed between the gate electrode 4 and the drain wirings 10 and being electrically connected to the source electrodes 3.

A method includes forming a source/drain region, forming a dielectric layer over the source/drain region, and etching the dielectric layer to form a contact opening. The source/drain region is exposed to the contact opening. The method further includes depositing a dielectric spacer layer extending into the contact opening, etching the dielectric spacer layer to form a contact spacer in the contact opening, implanting a dopant into the source/drain region through the contact opening after the dielectric spacer layer is deposited, and forming a contact plug to fill the contact opening.

A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a base substrate; gate structures and source/drain plugs over the base substrate; source/drain contact structures on the source/drain plugs; gate contact structures on the gate structures; and a dielectric layer on the gate structures and the source/drain plugs. Cavities are formed between the gate structures and the source/drain plugs along a surface of the base substrate. The dielectric layer encloses tops of the cavities.

A semiconductor device structure and a formation method are provided. The method includes forming a fin structure over a substrate. The fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner. The method also includes partially removing the fin structure to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers and forming multiple inner spacers covering the side surfaces of the sacrificial layers. The method further includes recessing the semiconductor layers from the side surfaces of the semiconductor layers after the inner spacers are formed and partially removing the inner spacers so that each of the inner spacers becomes thinner. In addition, the method includes forming an epitaxial structure on the side surfaces of the semiconductor layers.

Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a first source/drain feature and a second source/drain feature, a plurality of semiconductor layers vertically stacked and disposed between the first and second source/drain features, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, and an interfacial layer (IL) disposed between the gate electrode layer and one of the plurality of the semiconductor layers, wherein a topmost semiconductor layer of the plurality of the semiconductor layers has a first length, and the IL has a second length greater than the first length.

A method for forming a semiconductor device structure includes forming fin structures over a substrate. The method also includes depositing an isolation material surrounding the fin structures. The method also includes forming a dummy gate structure across the fin structure. The method also includes growing source/drain epitaxial structures over opposite sides of the dummy gate structure. The method also includes removing the dummy gate structure. The method also includes recessing the isolation material after removing the dummy gate structure. The method also includes forming a gate structure over the isolation material.

In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

The present disclosure describes a 2D channel FET with low contact resistance and a method for forming such a structure. The method includes depositing a dielectric layer on a semiconductor substrate, depositing a metal layer on the dielectric layer, and depositing a hard mask layer on the metal layer. The method further includes forming a gate opening by removing a portion of the hard mask layer and a portion of the metal layer. The method further includes depositing a spacer material layer on sidewalls of the gate opening and forming a channel, the channel including a TMC layer, at a bottom of the gate opening. The method further includes forming a gate structure on the channel and in the gate opening and removing the hard mask layer.

The present application discloses a semiconductor transistor structure, which includes: a substrate formed with a well region of a first conductive type, a gate structure being disposed on the substrate; a source/drain region of a second conductive type disposed in the well region of the first conductive type, the source region and the drain region being located on two sides of the gate structure respectively; a contact hole formed at a position corresponding to the source/drain region; and a conductive metal filled in the contact hole, the bottom of the contact hole being implanted with impurity ions for decreasing the contact resistance of the contact hole, and the impurity ion concentration at a peripheral region where the bottom of the contact hole comes into contact with the source/drain region being lower than the impurity ion concentration at a middle region.

A member includes a buffer layer made of GaN. The member is characterized in that the member includes a source layer arranged on top of the buffer layer, and the source layer made of n-doped GaN. The member includes a first barrier layer made of AlGaN arranged over the buffer layer and a first gate layer made of p-doped GaN arranged over the first barrier layer, where the first barrier layer and the first gate layer are arranged adjacent the source layer on one side. The member includes a second barrier layer made of AlGaN arranged over the buffer layer and a second gate layer made of p-doped GaN arranged over the second barrier layer, where the second barrier layer and the second gate layer are arranged adjacent the source layer on another side. The member enables an independent optimization of the two-dimensional electron gas characteristics and the threshold voltage.