A semiconductor device includes a gate structure that extends from a first surface into a semiconductor portion and that surrounds a transistor section of the semiconductor portion. A field plate structure includes a field electrode and extends from the first surface into the transistor section. A mesa section of the semiconductor portion separates the field plate structure and the gate structure. A contact structure includes a first portion directly adjoining the mesa section and a second portion directly adjoining the field electrode. The first and second portions include stripes and are directly connected to each other.

A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a gate, a spacer on a sidewall of the gate, a doping region on one side of the gate, an insulating cap layer covering the gate, the spacer and the doping region, and a redistributed contact layer (RCL) on the insulating cap layer. The RCL extends from the active area to the trench isolation region. A contact plug is disposed above the trench isolation region and is electrically connected to the gate or the doping region through the RCL.

A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervenes therebetween.

A display substrate comprises a base substrate and a first metal layer, a second metal layer, a first electrode pattern, a second electrode pattern, a first insulating layer and a second insulating layer formed above the base substrate. The first insulating layer is located over the first metal layer, the second insulating layer is located above the first insulating layer, the first electrode pattern and the second metal layer are located between the first insulating layer and the second insulating layer; a via hole is arranged at a position directly above the first metal layer to which the first insulating layer and the second insulating layer correspond, one end of the first electrode pattern is connected with the second metal layer, the other end extends into the via hole, the second electrode pattern is in the via hole and connected with the first electrode pattern and the first metal layer.

Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements (NCEM). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes, including GATE-snake-open and/or GATE-snake-resistance failure modes. Such wafers, chips, or dies may include Designs of Experiments (DOEs), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode.

One method disclosed herein includes performing a plurality of conformal deposition processes to form first, second and third layers of material within a contact opening, wherein the first layer comprises a contact insulating material, the second layer comprises a metal-containing material and the third layer comprises a conductive cap material, wherein the third layer is positioned above the second layer. The method further includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, forming a conductive material above the third layer and removing portions of the layers of material positioned outside of the contact opening.

An IC includes first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (NCEM). The first DOE contains fill cells configured to enable non-contact (NC) detection of tip-to-tip shorts, and the second DOE contains fill cells configured to enable NC detection of chamfer shorts.

A semiconductor device includes dummy gate structures formed on a dielectric layer over a substrate and forming a gap therebetween. A trench silicide structure is formed in the gap on the dielectric layer and extends longitudinally beyond the gap on end portions. The trench silicide structure forms a resistive element. Self-aligned contacts are formed through an interlevel dielectric layer and land on the trench silicide structure beyond the gap on the end portions.

The surface of an interlayer insulating film formed over an emitter coupling portion and the surface of an emitter electrode formed over the interlayer insulating film are caused to have a gentle shape, in particular, at the end of the emitter coupling portion, by forming the emitter coupling portion over a main surface of a semiconductor substrate and integrally with trench gate electrodes in order to form a spacer over the sidewall of the emitter coupling portion. Thereby, stress is dispersed, not concentrated in an acute angle portion of the emitter coupling portion when an emitter wire is coupled to the emitter electrode (emitter pad), and hence occurrence of a crack can be suppressed. Further, by forming the spacer, the concavities and convexities to be formed in the surface of the emitter electrode can be reduced, whereby the adhesiveness between the emitter electrode and the emitter wire can be improved.

An IC includes first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (NCEM). The first DOE contains fill cells configured to enable non-contact (NC) detection of via opens, and the second DOE contains fill cells configured to enable NC detection of metal island opens.