An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.

An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.

The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.

A laterally diffused metal oxide semiconductor (LDMOS) transistor structure with improved unclamped inductive switching immunity. The LDMOS includes a substrate and an adjacent epitaxial layer both of a first conductivity type. A gate structure is above the epitaxial layer. A drain region and a source region, both of a second conductivity type, are within the epitaxial layer. A channel is formed between the source and drain region and arranged below the gate structure. A body structure of the first conductivity type is at least partially formed under the gate structure and extends laterally under the source region, wherein the epitaxial layer is less doped than the body structure. A conductive trench-like feed-through element passes through the epitaxial layer and contacts the substrate and the source region. The LDMOS includes a tub region of the first conductivity type formed under the source region, and adjacent laterally to and in contact with said body structure and said trench-like feed-through element.

A semiconductor device includes a substrate, a plurality of fins on the substrate, wherein the plurality of fins each include a fin channel region, first isolation regions on the substrate corresponding to active gate regions, a second isolation region on the substrate corresponding to a dummy gate region, wherein a height of the second isolation region is greater than a height of the first isolation regions, a plurality of active gate structures formed around the fins, and on the first isolation regions, and a dummy gate structure formed on the second isolation region.

A metal oxide semiconductor based power device in 4H-SiC semiconductor includes a semiconductor region, a drain electrode disposed adjacent a drain region and a source electrode disposed adjacent a source region which is disposed over a base region, and a gate electrode separated from the semiconductor region by silicon dioxide as a dielectric material. To avoid punchthrough, when the channel has a length of between i) about 0.5 m and about 0.4 m, ii) about 0.4 m and about 0.3 m, iii) about 0.3 m and about 0.2 m, or iv) about 0.2 m and about 0.1 m, the silicon dioxide has a corresponding thickness range of between i) about 5 nm to about 25 nm, ii) about 5 nm to about 20 nm, iii) about 5 nm to about 15 nm, or iv) about 5 nm to about 10 nm, respectively each base region at a predetermined doping profile.

A semiconductor device includes: an n-type first source region and first drain region formed in a surface of a p-type epitaxial layer; an n-type first source drift region and first drain drift region formed so as to individually surround the first source region and the first drain region; and a p-type first diffusion region formed in a first channel region and having a higher concentration than the epitaxial layer, the semiconductor device having p-type first withstand voltage maintaining regions formed between the first diffusion region, and the first source drift region and first drain drift region respectively, the first withstand voltage maintaining regions having a lower concentration than the first diffusion region.

A method for fabricating a semiconductor device having a substantially undoped channel region includes performing an ion implantation into a substrate, depositing a first epitaxial layer over the substrate, and depositing a second epitaxial layer over the first epitaxial layer. In various examples, a plurality of fins is formed extending from the substrate. Each of the plurality of fins includes a portion of the ion implanted substrate, a portion of the first epitaxial layer, and a portion of the second epitaxial layer. In some embodiments, the portion of the second epitaxial layer of each of the plurality of fins includes an undoped channel region. In various embodiments, the portion of the first epitaxial layer of each of the plurality of fins is oxidized.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate has an active region. The semiconductor substrate is doped with first dopants with a first-type conductivity. The active region is adjacent to the first surface and doped with second dopants with a second-type conductivity. The semiconductor device structure includes a doped layer over the second surface and doped with third dopants with the first-type conductivity. A first doping concentration of the third dopants in the doped layer is greater than a second doping concentration of the first dopants in the semiconductor substrate. The semiconductor device structure includes a conductive bump over the doped layer.

Methods and apparatus for quantum point contacts. In an arrangement, a quantum point contact device includes at least one well region in a portion of a semiconductor substrate and doped to a first conductivity type; a gate structure disposed on a surface of the semiconductor substrate; the gate structure further comprising a quantum point contact formed in a constricted area, the constricted area having a width and a length arranged so that a maximum dimension is less than a predetermined distance equal to about 35 nanometers; a drain/source region in the well region doped to a second conductivity type opposite the first conductivity type; a source/drain region in the well region doped to the second conductivity type; a first and second lightly doped drain region in the at least one well region. Additional methods and apparatus are disclosed.