The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 11018 cm-3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.

Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided.

In an embodiment, a substrate structure includes a support substrate, a buffer structure arranged on the support substrate, the buffer structure including an intentionally doped superlattice laminate, an unintentionally doped first Group III nitride layer arranged on the buffer structure, a second Group III nitride layer arranged on the first Group III nitride layer forming a heterojunction therebetween, and a blocking layer arranged between the heterojunction and the buffer structure. The blocking layer is configured to block charges from entering the buffer structure.

A semiconductor device comprising: a first electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; a third semiconductor region of the second conductivity type provided between the first semiconductor region and the second semiconductor region on the first electrode and having a higher carrier concentration of the second conductivity type than the second semiconductor region; a fourth semiconductor region; a fifth semiconductor region; a sixth semiconductor region; a seventh semiconductor region; a gate electrode; a gate insulating layer; and a second electrode provided on the fifth semiconductor region and the seventh semiconductor region.

A plurality of gate structures are formed straddling nFET semiconductor fins and pFET semiconductor fins which extend upwards from a surface of a semiconductor substrate. A boron-doped silicon germanium alloy material is epitaxially grown from exposed surfaces of both the nFET semiconductor fins and the pFET semiconductor fins not protected by the gate structures. An anneal is then performed. During the anneal, silicon and germanium from the boron-doped silicon germanium alloy material diffuse into the nFET semiconductor fins and act as an n-type dopant forming a junction in the nFET semiconductor fins. Since boron is a Group IIIA element it does not have any adverse effect. During the same anneal, boron from the boron-doped silicon germanium alloy material will diffuse into the pFET semiconductor fins to form a junction therein.

The present invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; implanting a deuterium and hydrogen co-doping layer at a certain pre-determined depth of the first wafer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer; separating a part of the first wafer from the second wafer; and forming a deuterium and hydrogen co-doping semiconductor layer on the second wafer.

There is provided an MPS diode comprising a first semiconductor layer that is an N type; P-type semiconductor regions and N-type semiconductor regions that are arranged alternately on one surface of the first semiconductor layer; and a Schottky electrode that is in Schottky junction with the N-type semiconductor regions and is arranged to be adjacent to and in contact with at least part of the P-type semiconductor regions. A donor concentration in an area of the N-type semiconductor region that is adjacent to and in contact with the first semiconductor layer is lower than the donor concentration in an area of the first semiconductor layer that is adjacent to and in contact with the N-type semiconductor region and is lower than the donor concentration in an area of the N-type semiconductor region that is adjacent to and in contact with the Schottky electrode. This configuration improves a breakdown voltage under applying a reverse bias voltage and reduces a rising voltage under applying a forward bias voltage.

A semiconductor device includes a substrate, and a stacked portion over the substrate, the stacked structure including a first nitride semiconductor layer containing aluminum, a second nitride semiconductor layer containing carbon, and a third nitride semiconductor layer whose carbon concentration is lower than carbon concentration of the second nitride semiconductor layer. A fourth nitride semiconductor layer whose carbon concentration is lower than carbon concentration of the second nitride semiconductor layer and whose thickness is greater than the thickness of each of the first to third nitride semiconductor layers is provided on an upper surface of the stacked portion. A fifth nitride semiconductor layer containing aluminum is provided on an upper surface of the fourth nitride semiconductor layer. A first electrode is provided on an upper surface of the fifth nitride semiconductor layer.

A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.