A quantum device with semiconductor qubits, comprising at least: a layer of a first semiconductor arranged on a layer of a second semiconductor, the forbidden energy band of which is different from that of the first semiconductor, such that one of the layers forms a confinement potential barrier with respect to the electrons or the holes intended to be located in confinement regions formed in the other layer; cavities formed through only one portion of the thickness of the layer of the first semiconductor; and electrically conductive control gates at least partially arranged individually in one of the cavities.

A semiconductor device has a substrate with a diamond material. A surface of the substrate is prepared using a first reaction process. The first reaction process can be etching or polishing with oxygen and methane at a gas mixture ratio of about 1:2. The surface of the substrate is exposed to hydrogen plasma prior to the first reaction process. A diamond layer is formed over the surface of the substrate using a second reaction process. The second reaction process can be nucleation or epitaxial growth. The transition from the first reaction process to the second reaction process is seamless. The transition is seamless by nature of the second reaction process continuing from the first reaction process. The diamond layer can be formed over the surface of the substrate using a third reaction process, such as an epitaxial growth. A semiconductor device is formed in the substrate and diamond layer.

An object is to provide a technique that ensures to reduce a parasitic resistance of a semiconductor device while enhancing a breakdown voltage property of a semiconductor device. A portion of a second semiconductor layer exposed from a first semiconductor layer corresponds to a concave portion of a laminated structure and the first semiconductor layer or an adjacent portion of the first semiconductor layer and a second semiconductor layer corresponds to a convex portion of the laminated structure. A first guard ring of a second conductivity type is arranged on side walls of the convex portion, and in the concave portion, a guard ring of the second conductivity type is not arranged, or a second guard ring of the second conductivity type having a thickness thinner than that of the first guard ring is arranged.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a valley inwardly positioned on a top surface of the substrate; a programmable insulating layer conformally positioned on the valley and including a V-shaped cross-sectional profile; and a top electrode positioned on the programmable insulating layer. The programmable insulating layer is configured to be blown out under a programming voltage.

A method of forming an electrode in accordance with an exemplary embodiment includes a process of forming a mask pattern on one surface of a base to expose a partial area of the one surface of the base by using a mask material that is polymer including an end tail having at least one bonding structure of covalent bond and double bond, a process of loading the base on which the mask pattern is formed into a chamber, and a process of forming a conductive layer containing copper on the exposed one surface of the base by using an atomic layer deposition method that alternately injects a source material containing copper and a reactive material that reacts with the source material into the chamber. Thus, according to the method of forming an electrode in accordance with an exemplary embodiment, a thin-film caused by a material for forming an electrode is not formed on a surface of the mask pattern. Therefore, a residue is not remained when the mask pattern is removed to prevent a defect caused by the residue from being generated.

A method for manufacturing an SiC semiconductor device includes a step of setting, on a main surface of an SiC wafer, a scheduled cutting line that demarcates a plurality of chip regions including a first chip region in which a functional device is formed and a second chip region in which a monitor pattern for performing process control of the first chip region is formed, a step of forming, on the main surface, a plurality of main surface electrodes respectively covering the chip regions such as to expose the scheduled cutting line and respectively forming a portion of the functional device and a portion of the monitor pattern, a step of irradiating laser light to the scheduled cutting line and forming a modified region, and a step of cleaving the SiC wafer with the modified region as a starting point.

A method for manufacturing an SiC semiconductor device includes a step of setting, on a main surface of an SiC wafer, a scheduled cutting line that demarcates a plurality of chip regions including a first chip region in which a functional device is formed and a second chip region in which a monitor pattern for performing process control of the first chip region is formed, a step of forming, on the main surface, a plurality of main surface electrodes respectively covering the chip regions such as to expose the scheduled cutting line and respectively forming a portion of the functional device and a portion of the monitor pattern, a step of irradiating laser light to the scheduled cutting line and forming a modified region, and a step of cleaving the SiC wafer with the modified region as a starting point.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a valley inwardly positioned on a top surface of the substrate; a programmable insulating layer conformally positioned on the valley and including a V-shaped cross-sectional profile; and a top electrode positioned on the programmable insulating layer. The programmable insulating layer is configured to be blown out under a programming voltage.

A semiconductor device includes a first electrode, a first semiconductor layer of a first conductivity type on the first electrode, a first pillar of a second conductivity type on the first semiconductor layer, the first pillar having a first average concentration of impurities, a second pillar of the first conductivity type on the first semiconductor layer, and including a first layer having a second average concentration of impurities lower than the first average concentration, and a second layer having a third average concentration of impurities higher than the first average concentration, a second semiconductor layer of the second conductivity type on the second pillar, a third semiconductor layer of the first conductivity type on the second semiconductor layer, a second electrode connected to the first pillar and the third semiconductor layer, a third electrode, and an insulating film disposed between the second semiconductor layer and the third electrode.

A semiconductor device includes a first electrode, a first semiconductor layer of a first conductivity type on the first electrode, a first pillar of a second conductivity type on the first semiconductor layer, the first pillar having a first average concentration of impurities, a second pillar of the first conductivity type on the first semiconductor layer, and including a first layer having a second average concentration of impurities lower than the first average concentration, and a second layer having a third average concentration of impurities higher than the first average concentration, a second semiconductor layer of the second conductivity type on the second pillar, a third semiconductor layer of the first conductivity type on the second semiconductor layer, a second electrode connected to the first pillar and the third semiconductor layer, a third electrode, and an insulating film disposed between the second semiconductor layer and the third electrode.