A dual channel trench LDMOS transistor includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the second conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the first conductivity type formed in the body region and adjacent the first trench; a planar gate overlying the body region; a drain drift region of the first conductivity type formed in the semiconductor layer and in electrical contact with a drain electrode; and alternating N-type and P-type regions formed in the drain drift region with higher doping concentration than the drain-drift regions to form a super-junction structure in the drain drift region.

A semiconductor device includes: a semiconductor chip having a main surface; an output region formed over the main surface with output elements being arranged in the output region; an inner element region surrounded by the output region and insulated and isolated from the output region with a first element different from the output elements being arranged in the inner element region; a first wiring layer formed over the main surface so as to cover the output region, and including a first output wiring electrically connected to the output elements; and a second wiring layer formed over the first wiring layer, and including second output wirings electrically connected to the first output wiring and a connection wiring insulated and isolated from the second output wirings, the connection wiring extending across the output region from the inner element region to an outer region outside the output region.

A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device.

In one embodiment, a semiconductor device comprises a bulk semiconductor substrate that includes a first conductivity type floating buried doped region bounded above by a second conductivity type doped region and bounded below by another second conductivity semiconductor region. Dielectric isolation regions extend through the second conductivity doped region and the first conductivity floating buried doped region into the semiconductor region. Functional devices are disposed within the second conductivity type doped region. The first conductivity type floating buried doped region is configured as a self-biased region that laterally extends between adjacent dielectric isolation regions.

A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.

Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a method for forming a semiconductor device includes forming a first epitaxial layer on sidewalls of trenches and forming second epitaxial layer on the first epitaxial layer where charges in the doped regions along the sidewalls of the first and second trenches achieve charge balance in operation. In another embodiment, the semiconductor device includes a termination structure including an array of termination cells.

The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.

Components can be damaged if they are exposed to excess voltages. A device is disclosed herein which can be placed in series with a component and a node that may be exposed to high voltages. If the voltage becomes too high, the device can autonomously switch into a relatively high impedance state, thereby protecting the other components.

A semiconductor device according to an embodiment is provided with a plurality of active barrier sections each of which is enclosed by a plurality of element isolation sections each of which is configured of a closed pattern. Namely, the plurality of active barrier sections are electrically isolated from each other.

One aspect of this disclosure is a power amplifier module that includes a power amplifier die including a power amplifier configured to amplify a radio frequency (RF) signal, the power amplifier including a heterojunction bipolar transistor (HBT) and a p-type field effect transistor (PFET), the PFET including a semiconductor segment that includes substantially the same material as a layer of a collector of the HBT, the semiconductor segment corresponding to a channel of the PFET; a load line electrically connected to an output of the power amplifier and configured to provide impedance matching at a fundamental frequency of the RF signal; and a harmonic termination circuit electrically connected to the output of the power amplifier and configured to terminate at a phase corresponding to a harmonic frequency of the RF signal. Other embodiments of the module are provided along with related methods and components thereof.