Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.

Graphene is used as an interfacial layer to grow Si and other semiconductors or crystalline materials including two-dimensional Si and other structures on any foreign substrate that can withstand the growth temperature without the limitation matching condition typically required for epitaxial growth.

A Schottky barrier device is provided herein that includes a TMD layer on a substrate, a graphene layer on the TMD layer, an electrolyte layer on the TMD layer, and a source gate contact on the electrolyte layer. A drain contact can be provided on the TMD layer and a source contact can be provided on the graphene layer. As ionic gating from the source gate contact and electrolyte layer is used to adjust the Schottky barrier height this Schottky barrier device can be referred to as an ionic control barrier transistor or ionic barristor.

An apparatus and method, the apparatus comprising: at least one charged substrate (3); a channel of two dimensional material (5); and at least one floating electrode (7A-C) wherein the floating electrode comprises a first area (10A-C) adjacent the at least one charged substrate, a second area (11A-C) adjacent the channel of two dimensional material and a conductive interconnection (9A-C) between the first area and the second area wherein the first area is larger than the second area and wherein the at least one floating electrode is arranged to control the level of doping within the channel of two dimensional material.

Various methods for fabricating non-planar integrated circuit devices, such as FinFET devices, are disclosed herein. An exemplary method includes forming a rib structure extending from a substrate; forming a two-dimensional material layer (including, for example, transition metal dichalcogenide or graphene) on the rib structure and the substrate; patterning the two-dimensional material layer, such that the two-dimensional material layer is disposed on at least one surface of the rib structure; and forming a gate on the two-dimensional material layer. In some implementations, a channel region, a source region, and a drain region are defined in the two-dimensional material layer. The channel region is disposed between the source region and the drain region, where the gate is disposed over the channel region. In some implementations, the patterning includes removing the two-dimensional material layer disposed on a top surface of the substrate and/or disposed on a top surface of the rib structure.

A photodetector includes an insulating layer on a substrate, a first graphene layer on the insulating layer, a 2-dimensional (2D) material layer on the first graphene layer, a second graphene layer on the 2D material layer, a first electrode on the first graphene layer, and a second electrode on the second graphene layer. The 2D material layer includes a barrier layer and a light absorption layer. The barrier layer has a larger bandgap than the light absorption layer.

A laminated body includes: a substrate portion composed of silicon carbide; and a graphene film disposed on a first main surface of the substrate portion, the graphene film having an atomic arrangement oriented with respect to an atomic arrangement of the silicon carbide of the substrate portion. A region in which a value of G/G in Raman spectrometry is not less than 1.2 is not less than 10% in an area ratio in an exposed surface of the graphene film, the exposed surface being a main surface of the graphene film opposite to the substrate portion.

A structure is provided that comprises a substrate, a plurality of elements, and a plurality of trenches disposed on the substrate. Each element is separated from adjacent elements by a trench in the plurality of trenches and has a top surface with a first and an opposing second side. A first portion of the top surface is on the first side and a second portion of the top surface is on the opposing second side. The structure further comprises a plurality of first graphene layers, each of which is formed on the first portion of the top surface of an element in the plurality of elements. The structure further comprises a plurality of second graphene layers, each of which is formed on the second portion of the top surface of a corresponding element so that each element is separately overlayed by a first graphene layer and a second graphene layer.

A detector for detecting single photons of infrared radiation or longer wavelength electromagnetic radiation. In one embodiment a waveguide configured to transmit infrared radiation is arranged to be adjacent a graphene sheet and configured so that evanescent waves from the waveguide overlap the graphene sheet. In other embodiments a transmission line or antenna is coupled to the graphene sheet and guides longer-wavelength photons to the graphene sheet. A photon absorbed by the graphene sheet heats the graphene sheet. Part of the graphene sheet is part of the Josephson junction as the weak link, and a constant bias current is driven through the Josephson junction; an increase in the temperature of the graphene sheet results in a decrease in the critical current of the Josephson junction and a voltage pulse in the voltage across the Josephson junction. The voltage pulse is detected by the pulse detector.

The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.