A semiconductor device includes: a semiconductor substrate; a main electrode; a peripheral electrode; an insulating protective film; a surface metallic layer; and a solder layer, wherein the semiconductor substrate includes: a first region of a first conductive-type in contact with the main electrode on a main contact surface; a second region of a first conductive-type in contact with the peripheral electrode on a peripheral contact surface; and a third region of a second conductive-type provided under the first region, under the second region, and circumferentially outward of the second region, and a circumferentially-outward end of the metallic layer and a circumferentially-outward end of the solder layer are located more circumferentially inward than the circumferentially-outward end of the peripheral electrode.

In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type field-stop layer together with the total impurity of an n.sup. type drift layer. Also, the n-type field-stop layer can have a concentration gradient such that the impurity concentration of the n-type field-stop layer decreases from a p.sup.+ type collector layer toward a p-type base layer, and the diffusion depth is 20 m or more. Furthermore, an n.sup.+ type buffer layer of which the peak impurity concentration can be higher than that of the n-type field-stop layer at 610.sup.15 cm.sup.3 or more, and one-tenth or less of the peak impurity concentration of the p.sup.+ type collector layer, can be included between the n-type field-stop layer and p.sup.+ type collector layer.

The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage V.sub.th of 0.3 V to 0.7 V and a leakage current J.sub.r of 110.sup.9 A/cm.sup.2 to 110.sup.4 A/cm.sup.2 in a rated voltage V.sub.R.

An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p.sup.+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p.sup.+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

A wide band gap semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer, first, second, and third regions having particular conductivity types and defining sides of the trench, and a first electrode embedded inside an insulating film in the trench. The second region integrally includes a first portion arranged closer to a first surface of the semiconductor layer than to a bottom surface of the trench, and a second portion projecting from the first portion toward a second surface of the semiconductor layer to a depth below a bottom surface of the trench. The second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.

High voltage devices and methods for forming a high voltage device are disclosed. The method includes providing a substrate having top and bottom surfaces. The substrate is defined with a device region and a recessed region disposed within the device region. The recessed region includes a recessed surface disposed lower than the top surface of the substrate. A transistor is formed over the substrate. Forming the transistor includes forming a gate at least over the recessed surface and forming a source region adjacent to a first side of the gate below the recessed surface. Forming the transistor also includes forming a drain region displaced away from a second side of the gate. First and second device wells are formed in the substrate within the device region. The first device well encompasses the drain region and the second device well encompasses the source region.

A semiconductor device and manufacturing method achieve miniaturization, prevent rise in threshold voltage and on-state voltage, and prevent decrease in breakdown resistance. N.sup.+-type emitter region and p.sup.++-type contact region are repeatedly alternately disposed in a first direction in which a trench extends in stripe form in a mesa portion sandwiched between trench gates. P.sup.+-type region covers an end portion on lower side of junction interface between n.sup.+-type emitter region and p.sup.++-type contact region. Formation of trench gate structure is such that n.sup.+-type emitter region is selectively formed at predetermined intervals in the first direction in the mesa portion by first ion implantation. P.sup.+-type region is formed less deeply than n.sup.+-type emitter region in the entire mesa portion by second ion implantation. The p.sup.++-type contact region is selectively formed inside the p+-type region by third ion implantation. N.sup.+-type emitter region and p.sup.++-type contact region are diffused and brought into contact.

A method of forming a semiconductor device that may include etching source and drain portions of a fin structure of a first semiconductor material selectively to an underlying semiconductor layer of a second semiconductor material, and laterally etching undercut region in the semiconductor layer underlying the fin structure. The method may further include filling the undercut region with a first conductivity type semiconductor material, and forming a second conductivity type semiconductor material for a source region and a drain region on opposing sides of the channel region portion of the fin structure.

A MOS gate structure is provided on a p-type base layer side of a silicon carbide semiconductor base formed by sequentially forming on a front surface of an n.sup.+-type silicon carbide substrate, an n-type drift layer and a p-type base layer by epitaxial growth. On the base front surface, in an edge termination structure region, a step portion occurring between the p-type base layer and the n-type drift layer, and a flat portion farther outward than the step portion are provided. In a surface layer of the n-type drift layer, a p.sup.+-type base region constituting the MOS gate structure is provided so as to contact the p-type base layer. The outermost p.sup.+-type base region extends from an active region into the flat portion and the entire lower side of this portion is covered by an innermost p.sup.-type region constituting an edge termination structure provided in the flat portion.

To improve withstand capability of a semiconductor device during reverse recovery, provided is a semiconductor device including a semiconductor substrate having a first conduction type; a first region having a second conduction type that is formed in a front surface of the semiconductor substrate; a second region having a second conduction type that is formed adjacent to the first region in the front surface of the semiconductor substrate and has a higher concentration than the first region; a third region having a second conduction type that is formed adjacent to the second region in the front surface of the semiconductor substrate and has a higher concentration than the second region; an insulating film that covers a portion of the second region and the third region; and an electrode connected to the second region and the first region that are not covered by the insulating film.